公开(公告)号：US5600815A

公开(公告)日：1997-02-04

申请号：US469928

申请日：1995-06-06

Applicant: Chong M. Lin ,  Raymond J. Werner

Inventor： Chong M. Lin ,  Raymond J. Werner

IPC: G06F3/06 ,  G06F5/06 ,  G06F5/16 ,  G11C7/10 ,  G06F13/16 ,  G06F13/12

CPC classification number: G06F5/16 ,  G06F3/0601 ,  G06F3/0608 ,  G06F3/0656 ,  G06F3/0679 ,  G06F5/06 ,  G11C19/28 ,  G11C7/1036 ,  G06F2003/0691

Abstract: A buffer memory architecture, method, and chip floor plan allows for significant reduction in the physical area required for a buffer memory of any given size in a microelectronic device. Buffer applications wherein random access to the buffered data is not required use a CMOS dynamic serial memory with p-channel devices supplied with a voltage less positive than the voltage supplied to their respective n-wells. In a particular embodiment, three memory stages are used in a cascaded fashion. The first and third memory stages store data on a parallel basis, while the second memory stage stores data on a serial basis. The second memory stage can be fabricated using much less chip area per bit than the first and third memory stages. Significant area reduction is achieved because the second memory stage eliminates addressing overhead associated with conventional high-density memory schemes, and low voltage power supplies permit relaxation of latch-up prevention layout rules.

Abstract translation: 缓冲存储器架构，方法和芯片平面图允许显微减少微电子器件中任何给定尺寸的缓冲存储器所需的物理区域。 不需要对缓冲数据进行随机访问的缓冲应用程序使用具有提供的电压小于提供给其相应n阱的电压的正电压的p沟道器件的CMOS动态串行存储器。 在特定实施例中，以级联方式使用三个存储器级。 第一和第三存储器级以并行方式存储数据，而第二存储器级以串行方式存储数据。 可以使用比第一和第三存储器级更少的每位芯片面积制造第二存储器级。 实现了显着的面积减小，因为第二存储器级消除了与常规高密度存储器方案相关联的寻址开销，并且低压电源允许松开防闩锁布局规则。

公开(公告)号：US5381378A

公开(公告)日：1995-01-10

申请号：US128235

申请日：1993-09-29

Applicant: Yasunori Okimura

Inventor： Yasunori Okimura

IPC: G11C19/00 ,  G11C7/10 ,  G11C19/28 ,  G11C8/04

CPC classification number: G11C7/1036

Abstract: A semiconductor memory circuit includes a memory cell array for storing data, and a bit structure selection circuit for performing a data transfer between the memory cell array and an external device by constructing the data in units of one bit or in units of two bits. The bit structure selection circuit includes a selector for selectively modifying a phase of a first clock signal and a second clock signal in response to a mode signal, and shift register for modifying a shift width of a memory selection signal in response to the first clock signal and the second clock signal supplied through the selector.

Abstract translation: 半导体存储器电路包括用于存储数据的存储单元阵列，以及用于通过以1位或2位为单位构成数据来执行存储单元阵列与外部设备之间的数据传输的位结构选择电路。 比特结构选择电路包括：选择器，用于响应于模式信号选择性地修改第一时钟信号和第二时钟信号的相位;以及移位寄存器，用于响应于第一时钟信号修改存储器选择信号的移位宽度 并且通过选择器提供第二时钟信号。

公开(公告)号：US5371714A

公开(公告)日：1994-12-06

申请号：US26225

申请日：1993-02-26

Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

IPC: G11C7/10 ,  G11C8/14 ,  G11C8/18 ,  G11C8/00

CPC classification number: G11C8/14 ,  G11C7/1036 ,  G11C7/1039 ,  G11C8/18 ,  H01L2924/01074

Abstract: In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifier are made different for each subblock in the block in which the selected word line is included, whereby the peak current associated with the bit line charge/discharge at the time of activating the sense amplifiers is reduced.

Abstract translation: 在其中存储单元阵列被划分成多个块并且通过块单元执行数据输入/输出的块存取存储器中，每个块被划分成多个子块，并且激活字线和 激活读出放大器的定时对于其中包括所选择的字线的块中的每个子块而言是不同的，从而降低与激活读出放大器时的位线充电/放电相关联的峰值电流。

公开(公告)号：US4864402A

公开(公告)日：1989-09-05

申请号：US64013

申请日：1987-06-19

Applicant: Norio Ebihara ,  Takayuki Sasaki ,  Hiroyuki Kita ,  Yoshihito Ohsawa

Inventor： Norio Ebihara ,  Takayuki Sasaki ,  Hiroyuki Kita ,  Yoshihito Ohsawa

IPC: G11C7/10 ,  H04N5/907 ,  H04N9/877

CPC classification number: G11C7/1036 ,  H04N5/907 ,  H04N9/877

Abstract: A video memory, for use with a video tape recorder, a television receiver of the like to process a picture, is simplified and can achieve the functions of a time base corrector, a noise reducer and a comb filter, so as to considerably improve the quality of a video picture. A frequency converting circuit for use with the video memory includes a comparator for comparing first and second address signals and an address correction circuit connected to receive an output signal from the comparator. When a crossing occurs between the first and second address signals, the sequential order in which an address signal is supplied to the memory is switched by the address correcting circuit, to thereby derive a continuous output signal from the memory.

Abstract translation: 用于录像机的视频存储器，类似于其的处理图像的电视接收机被简化，可以实现时基校正器，降噪器和梳状滤波器的功能，从而显着改善 视频图片的质量。 用于视频存储器的频率转换电路包括用于比较第一和第二地址信号的比较器和连接以从比较器接收输出信号的地址校正电路。 当在第一和第二地址信号之间发生交叉时，由地址校正电路切换提供给存储器的地址信号的顺序，从而从存储器导出连续的输出信号。

公开(公告)号：US4845670A

公开(公告)日：1989-07-04

申请号：US15348

申请日：1987-02-17

Applicant: Toshio Nishimoto ,  Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta

Inventor： Toshio Nishimoto ,  Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta

IPC: G11C19/28 ,  G11C7/10 ,  G11C19/00

CPC classification number: G11C7/1036

Abstract: In a memory device, a shift-register comprises a plurality of stages for transferring sequentially a pair of signals which have mutually opposite phases. Each stage has a comparator circuit which compares the pair of signals and generates a pair of fixed voltage signals. By this construction, high-speed operation of the memory device, low power consumptions, and high-capacity load driving are achieved.

Abstract translation: 在存储装置中，移位寄存器包括用于顺序地传送具有相反相位的一对信号的多个级。 每个级具有比较器电路，其比较该对信号并产生一对固定电压信号。 通过这种结构，实现了存储器件的高速运行，低功耗和高容量负载驱动。

公开(公告)号：US4773045A

公开(公告)日：1988-09-20

申请号：US788000

申请日：1985-10-16

Applicant: Junji Ogawa

Inventor： Junji Ogawa

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/40 ,  G11C11/401 ,  G11C11/4096 ,  G11C11/41 ,  G11C19/00 ,  G11C19/28

CPC classification number: G11C7/1036 ,  G11C11/4096 ,  G11C7/1006

Abstract: A semiconductor memory device including a RAM portion and a shift register for enabling parallel transfer of a one word line amount of data of the RAM portion between the RAM portion and the shift register. The shift register is divided into a plurality of shift register portions with serial input data being distributed alternately between the shift register portions by the operation of a multiplexer and serial output data being obtained by picking up data alternately from the shift register portions by the operation of another multiplexer. A transfer gate portion is inserted between the RAM portion and the shift register for carrying out parallel transfer, the transfer gate portion includes a plurality of groups of transfer gates for enabling selective connections of input and output terminals of each of the stages of the shift register portions with either of the adjacent odd numbered bit line and even numbered bit line of the RAM portion. The plurality of transfer gate groups are switched in correspondence with shift clock signals.

Abstract translation: 一种半导体存储器件，包括RAM部分和移位寄存器，用于使RAM部分和移位寄存器之间的RAM部分的一个字线数据量的并行传送。 移位寄存器被分成多个移位寄存器部分，其中串行输入数据通过多路复用器的操作交替地分配在移位寄存器部分之间，串行输出数据是通过操作从移位寄存器部分交替地拾取数据而获得的 另一个多路复用器。 传输门部分插在RAM部分和移位寄存器之间，用于进行并行传输，传输门部分包括多组传输门，用于使移位寄存器的每个级的输入和输出端的选择性连接 与RAM部分相邻的奇数位线和偶数位线中的任一个的部分。 根据移位时钟信号切换多个传送门组。

公开(公告)号：US4630295A

公开(公告)日：1986-12-16

申请号：US633989

申请日：1984-07-24

Applicant: Setsufumi Kamuro ,  Takaaki Hirano ,  Mikiro Okada

Inventor： Setsufumi Kamuro ,  Takaaki Hirano ,  Mikiro Okada

IPC: G11C19/28 ,  G11C7/10 ,  G11C19/00 ,  H03M9/00 ,  G11C7/00

CPC classification number: G11C19/00 ,  G11C7/1036

Abstract: A serial input/output device includes a CMOS shift register having a plurality of D-type flip-flops. A detection circuit is associated with the CMOS shift register in order to detect whether the transfer data exists in the CMOS shift register. A gate circuit is provided for applying a transfer clock signal to the CMOS shift register only when the transfer data exists in the CMOS shift register, thereby minimizing the power consumption.

Abstract translation: 串行输入/输出装置包括具有多个D型触发器的CMOS移位寄存器。 检测电路与CMOS移位寄存器相关联，以检测CMOS移位寄存器中是否存在传输数据。 仅在CMOS移位寄存器中存在传输数据时才提供用于将传输时钟信号施加到CMOS移位寄存器的门电路，从而使功耗最小化。

公开(公告)号：US20240036877A1

公开(公告)日：2024-02-01

申请号：US18448079

申请日：2023-08-10

Applicant: Lodestar Licensing Group, LLC

Inventor： Kyle B. Larson ,  Richard C. Murphy ,  Troy A. Manning ,  Dean A. Klein

IPC: G06F9/38 ,  G06F15/78 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G06F9/3877 ,  G06F15/7821 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4087 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：US11843388B2

公开(公告)日：2023-12-12

申请号：US17647739

申请日：2022-01-12

Applicant: NXP B.V.

Inventor： Johannes Petrus Antonius Frambach ,  Cornelis Klaas Waardenburg ,  Gerard Arie de Wit

IPC: H04L7/00 ,  H03L7/099 ,  G11C7/10 ,  G11C7/16 ,  H03L7/081 ,  H03L7/085

CPC classification number: H03L7/0991 ,  G11C7/1036 ,  G11C7/16 ,  H03L7/081 ,  H03L7/085

Abstract: A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).

公开(公告)号：US20230386550A1

公开(公告)日：2023-11-30

申请号：US18202659

申请日：2023-05-26

Applicant: Micron Technology, Inc.

Inventor： Perry V. Lea ,  Glen E. Hush

IPC: G11C11/406 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4096 ,  G11C5/02 ,  G06F3/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093

CPC classification number: G11C11/40615 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/4096 ,  G11C7/1036 ,  G11C5/025 ,  G06F3/061 ,  G06F3/0616 ,  G06F3/0629 ,  G06F3/0673 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2211/4013 ,  G11C11/4094

Abstract: The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.