公开(公告)号：US20240120956A1

公开(公告)日：2024-04-11

申请号：US18463174

申请日：2023-09-07

Applicant: NXP B.V.

Inventor： Johannes Petrus Antonius Frambach ,  Cornelis Klaas Waardenburg ,  Stefan Paul van den Hoek ,  Gerard Arie de Wit

IPC: H04B1/04 ,  H04L12/40

CPC classification number: H04B1/04 ,  H04L12/40 ,  H04L2012/40215

Abstract: A transmitter circuit including an impedance setting circuit having first and second legs, wherein each leg includes an adjustable pull-up resistance and an adjustable pull-down resistance connected in series between a supply terminal and a reference terminal. A first-leg-node, between the adjustable resistances of the first leg, is connected to a first bus terminal. A second-leg-node, between the adjustable resistances of the second leg, is connected to a second bus terminal. The controller detects a transition in a transmission data signal, and in response to a dominant to recessive transition the controller controls a voltage setting circuit to set the differential driver voltage on the bus to a recessive value; adjusts each of the adjustable pull-up resistances and the adjustable pull-down resistances with the same target impedance profile such that the transmitter circuit drives the bus with a target driver impedance for an active recessive period of a bit time.

公开(公告)号：US11843388B2

公开(公告)日：2023-12-12

申请号：US17647739

申请日：2022-01-12

Applicant: NXP B.V.

Inventor： Johannes Petrus Antonius Frambach ,  Cornelis Klaas Waardenburg ,  Gerard Arie de Wit

IPC: H04L7/00 ,  H03L7/099 ,  G11C7/10 ,  G11C7/16 ,  H03L7/081 ,  H03L7/085

CPC classification number: H03L7/0991 ,  G11C7/1036 ,  G11C7/16 ,  H03L7/081 ,  H03L7/085

Abstract: A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).

公开(公告)号：US12224781B2

公开(公告)日：2025-02-11

申请号：US18463174

申请日：2023-09-07

Applicant: NXP B.V.

Inventor： Johannes Petrus Antonius Frambach ,  Cornelis Klaas Waardenburg ,  Stefan Paul van den Hoek ,  Gerard Arie de Wit

IPC: H04B1/04 ,  H04L12/40

Abstract: A transmitter circuit including an impedance setting circuit having first and second legs, wherein each leg includes an adjustable pull-up resistance and an adjustable pull-down resistance connected in series between a supply terminal and a reference terminal. A first-leg-node, between the adjustable resistances of the first leg, is connected to a first bus terminal. A second-leg-node, between the adjustable resistances of the second leg, is connected to a second bus terminal. The controller detects a transition in a transmission data signal, and in response to a dominant to recessive transition the controller controls a voltage setting circuit to set the differential driver voltage on the bus to a recessive value; adjusts each of the adjustable pull-up resistances and the adjustable pull-down resistances with the same target impedance profile such that the transmitter circuit drives the bus with a target driver impedance for an active recessive period of a bit time.

公开(公告)号：US20220247416A1

公开(公告)日：2022-08-04

申请号：US17647739

申请日：2022-01-12

Applicant: NXP B.V.

Inventor： Johannes Petrus Antonius Frambach ,  Cornelis Klaas Waardenburg ,  Gerard Arie de Wit

IPC: H03L7/099 ,  H03L7/081 ,  H03L7/085 ,  G11C7/10 ,  G11C7/16

Abstract: The disclosure relates to a Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).