公开(公告)号：US20180279432A1

公开(公告)日：2018-09-27

申请号：US15919147

申请日：2018-03-12

Applicant: ARKALUMEN INC.

Inventor： Gerald Edward BRIGGS

IPC: H05B33/08 ,  F21S4/20 ,  F21V23/00 ,  F21K99/00 ,  F21V23/04

CPC classification number: H05B33/0827 ,  F21K9/60 ,  F21K99/00 ,  F21S4/20 ,  F21V23/005 ,  F21V23/04 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/62 ,  H01L2924/0002 ,  H05B33/0803 ,  H05B33/0845 ,  H05B33/0857 ,  H05K1/05 ,  H05K2201/09309 ,  H05K2201/09972 ,  H05K2201/10106 ,  H01L2924/00

Abstract: A LED based lighting apparatus is disclosed. The light engine used in the lighting apparatus may use printed circuit board and have a plurality of LED groups that are independently controllable by a control unit. The power supply input and return paths connected to each LED group may be implemented on different layers to allow a compact footprint that may be used with traditional fluorescent encasements with relatively little modification. The LEDs may comprise a subset of LEDs having a first colour and a subset of LEDs having a second colour different from said first colour intertwined on the light engine.

公开(公告)号：US09942977B2

公开(公告)日：2018-04-10

申请号：US14810920

申请日：2015-07-28

Applicant: Yazaki Corporation

Inventor： Masashi Suzuki

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0209 ,  H05K1/0201 ,  H05K1/0207 ,  H05K1/181 ,  H05K2201/09972

Abstract: A heatsink-less electronic unit includes a metal coreless electronic substrate, a heatsink-less microcomputer and various semiconductor relays. The heatsink-less microcomputer and the various semiconductor relays are mounted on the metal coreless electronic substrate. The heatsink-less microcomputer is arranged on the metal coreless electronic substrate. Among the various semiconductor relays, the one which may reach the highest temperature is separated at a longest distance from a location where the heatsink-less microcomputer is arranged, and the various semiconductor relays are arranged separately from one another.

公开(公告)号：US20180098417A1

公开(公告)日：2018-04-05

申请号：US15499657

申请日：2017-04-27

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Bernhard Gebauer ,  Oliver Wiedenmann ,  Sarah Haney ,  Lueder Elbrecht ,  Deog-Soon Choi ,  Aaron Lee

IPC: H05K1/02 ,  H05K1/16 ,  H05K3/30 ,  H01F27/28 ,  H01F41/04

CPC classification number: H05K1/0216 ,  H01F27/2804 ,  H01F41/041 ,  H01F2027/2809 ,  H05K1/023 ,  H05K1/165 ,  H05K3/30 ,  H05K2201/09972 ,  H05K2201/10287 ,  H05K2201/1056

Abstract: Electrically-conductive wires are used to construct an EMI shield between inductors of an RF module that prevents, or at least reduces, EMI crosstalk between the inductors while maintaining high Q factors for the inductors. The EMI shield comprises at least a first set of electrically-conductive wires that at least partially surrounds and extends over at least a first inductor of a pair of inductors. Adjacent wires of the first set are spaced apart from one another by a predetermined distance selected to ensure that the EMI shield attenuates a frequency or frequency range of interest. First and second ends of each of the wires are connected to an electrical ground structure. A length of each wire in between the first and second ends of the respective wire extends above the first inductor and is spaced apart from the first inductor so as not to be in contact with the first inductor.

公开(公告)号：US09924600B2

公开(公告)日：2018-03-20

申请号：US14763493

申请日：2014-01-24

Applicant: THALES

Inventor： Christian Maudet

IPC: H05K1/16 ,  H05K3/02 ,  H05K1/18 ,  H05K3/46 ,  H05K3/00 ,  H05K3/30 ,  H05K3/36 ,  H05K1/02

CPC classification number: H05K3/027 ,  H05K1/0243 ,  H05K1/186 ,  H05K3/0047 ,  H05K3/30 ,  H05K3/36 ,  H05K3/4611 ,  H05K3/4694 ,  H05K2201/09972 ,  Y10T29/49128

Abstract: A process for manufacturing a printed circuit board, comprising a first main circuit board having a first structure, comprises steps suitable for inserting one or more secondary printed circuit boards having a different structure from that of the main printed circuit board, comprising: defining one or more cavities suitable for receiving the one or more inserts; preparing the one or more inserts comprising, on at least one side intended to make contact with a wall of the cavity, etched features and a metallization, and one or more vias; inserting the one or more inserts into the one or more cavities in the main circuit board; placing a resin in the one or more cavities to ensure cohesion of the assembly formed by the main circuit board and the one or more secondary circuit boards; laminating the assembly formed by the one or more inserts placed in the main circuit board.

公开(公告)号：US20180019237A1

公开(公告)日：2018-01-18

申请号：US15714712

申请日：2017-09-25

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro KURITA ,  Masaya KAWANO ,  Koji SOEJIMA

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L21/683 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

公开(公告)号：US09848500B2

公开(公告)日：2017-12-19

申请号：US15186022

申请日：2016-06-17

Applicant: SONY CORPORATION

Inventor： Thomas Merkle ,  Stefan Koch ,  Joo-Young Choi

IPC: H01L25/00 ,  H05K3/46 ,  H05K1/02 ,  H05K1/18 ,  H01L23/66 ,  H01L25/16 ,  H01L23/498 ,  H01L23/538 ,  H05K3/30 ,  H05K1/16

CPC classification number: H05K3/4697 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/66 ,  H01L25/16 ,  H01L2223/6616 ,  H01L2223/6633 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2924/0002 ,  H05K1/0243 ,  H05K1/16 ,  H05K1/185 ,  H05K3/301 ,  H05K3/465 ,  H05K2201/0715 ,  H05K2201/0723 ,  H05K2201/09972 ,  H05K2201/09981 ,  H05K2203/1469 ,  H01L2924/00

Abstract: The present invention relates to the field of integrating electronic systems that operate at mm-wave and THz frequencies. A monolithic multichip package, a carrier structure for such a package as well as manufacturing methods for manufacturing such a package and such a carrier structure are proposed to obtain a package that fully shields different functions of the mm-wave/THz system. The package is poured into place by polymerizing photo sensitive monomers. It gradually grows around and above the MMICs (Monolithically Microwave Integrated Circuit) making connection to the MMICs but recessing the high frequency areas of the chip. The proposed approach leads to functional blocks that are electromagnetically completely shielded. These units can be combined and cascaded according to system needs.

公开(公告)号：US09847325B2

公开(公告)日：2017-12-19

申请号：US15354484

申请日：2016-11-17

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L21/4763 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/18 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

公开(公告)号：US20170207026A1

公开(公告)日：2017-07-20

申请号：US15395059

申请日：2016-12-30

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Kunio IWAKOSHI ,  Seiji GOTO

IPC: H01G4/30 ,  B32B37/10 ,  H01G4/12 ,  B32B18/00 ,  H05K3/12 ,  H01G4/005

CPC classification number: H01G4/308 ,  B32B18/00 ,  B32B27/08 ,  B32B38/145 ,  B32B2250/24 ,  B32B2255/10 ,  B32B2255/205 ,  B32B2255/28 ,  B32B2307/202 ,  B32B2307/732 ,  B32B2315/02 ,  B32B2457/08 ,  B32B2457/16 ,  C04B2235/606 ,  H01G4/005 ,  H01G4/12 ,  H05K3/125 ,  H05K3/4629 ,  H05K2201/09972

Abstract: An electrode pattern forming method capable of forming an electrode pattern having a desired thickness in each of a plurality of areas on an identical surface by an ink-jet method is provided. In a method of forming an electrode pattern including a first conductive portion and a second conductive portion connected with each other onto a work piece by an ink-jet method, a first area corresponding to at least part of the first conductive portion and a second area corresponding to at least part of the second conductive portion are defined on an identical surface of the work piece, conductive ink droplets are ejected toward the first area and the second area to form the first conductive portion and the second conductive portion, and a resolution of conductive ink droplets differs between the first area and the second area.

公开(公告)号：US09596766B2

公开(公告)日：2017-03-14

申请号：US14173554

申请日：2014-02-05

Applicant: Intel Corporation

Inventor： David N. Shykind ,  James A. McCall

IPC: H05K3/02 ,  H05K3/10 ,  H05K1/03 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K3/10 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/0366 ,  H05K3/0052 ,  H05K2201/0187 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09972 ,  H05K2203/1554 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49798 ,  Y10T428/24058 ,  Y10T428/24917 ,  Y10T428/249935 ,  Y10T428/24994 ,  Y10T428/249943 ,  Y10T428/249946 ,  Y10T442/2926 ,  Y10T442/2992 ,  Y10T442/3065

Abstract: A method of manufacturing a circuit board is described herein. The method may include adding a resin, forming first and second fiberglass fibers, and forming first and second signal line traces capable of transmitting electrical signals. In some examples, a ratio between fiberglass and resin material near the first signal line trace is similar to a ratio between fiberglass and resin material near the second signal line trace. In some examples, the first and second fiberglass fibers diagonally cross near the first and second signal line traces. In some examples, the first and second fiberglass fibers cross near the first and second signal line traces in a zig-zag pattern.

Abstract translation: 这里描述了制造电路板的方法。 该方法可以包括添加树脂，形成第一和第二玻璃纤维纤维，以及形成能够传输电信号的第一和第二信号线迹线。 在一些实例中，第一信号线迹线附近的玻璃纤维和树脂材料之间的比率类似于第二信号线迹线附近的玻璃纤维和树脂材料之间的比率。 在一些示例中，第一和第二玻璃纤维光纤在第一和第二信号线迹线附近对角地交叉。 在一些示例中，第一和第二玻璃纤维纤维以锯齿形图案在第一和第二信号线迹线附近交叉。

公开(公告)号：US09560768B2

公开(公告)日：2017-01-31

申请号：US14634972

申请日：2015-03-02

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yasuhiko Kusama ,  Hideyuki Tako ,  Kenji Kawai ,  Fumihisa Miyasaka

IPC: H05K1/16 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/185 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15313 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/09972

Abstract: A wiring substrate includes a core layer having a hole penetrating therethrough in a thickness direction thereof, and having a projecting part projecting from an inner wall of the hole toward an inner space of the hole, the projecting part being situated at a border that divides a plurality of areas in the hole, a plurality of electronic components disposed in the areas, respectively, the electronic components being arranged at a spaced interval with the projecting part therebetween, and a resin layer filling the hole and supporting the electronic components, wherein a thickness of the projecting part in the thickness direction of the core layer decreases toward a tip of the projecting part.

Abstract translation: 布线基板包括芯层，该芯层在其厚度方向上具有贯穿其中的孔，并且具有从孔的内壁朝向孔的内部空间突出的突出部分，突出部分位于边界处， 所述孔中的多个区域，分别设置在所述区域中的多个电子部件，所述电子部件以与所述突出部分间隔的间隔布置，以及填充所述孔并支撑所述电子部件的树脂层，其中， 在芯层的厚度方向上的突出部分朝向突出部分的尖端减小。