公开(公告)号：US11481013B2

公开(公告)日：2022-10-25

申请号：US16880167

申请日：2020-05-21

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Efraim Rotem ,  Eliezer Weissmann ,  Avinash N. Ananthakrishnan ,  Dorit Shapira

IPC: G06F15/76 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3293 ,  G06F30/34 ,  G06F119/06 ,  G06F119/08

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US11436118B2

公开(公告)日：2022-09-06

申请号：US16728617

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Omer Barak ,  Rajshree Chabukswar ,  Russell Fenger ,  Eugene Gorbatov ,  Monica Gupta ,  Julius Mandelblat ,  Nir Misgav ,  Efraim Rotem ,  Ahmad Yasin

IPC: G06F11/34 ,  G06F9/48 ,  G06F9/50 ,  G06F9/455 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

公开(公告)号：US11436018B2

公开(公告)日：2022-09-06

申请号：US17124813

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Mark Charney ,  Michael Mishaeli ,  Robert Valentine ,  Itai Ravid ,  Jason W. Brandt ,  Gilbert Neiger ,  Baruch Chaikin ,  Efraim Rotem

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20220214738A1

公开(公告)日：2022-07-07

申请号：US17706118

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

IPC: G06F1/3206 ,  G06F1/3203 ,  G06F1/26

Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

公开(公告)号：US11307628B2

公开(公告)日：2022-04-19

申请号：US15589769

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/3203 ,  G06F1/26

Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210406060A1

公开(公告)日：2021-12-30

申请号：US16912770

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Eliezer Weissmann ,  Hisham Abu Salah ,  Rajshree Arun Chabukswar ,  Russell Jerome Fenger ,  Eugene Gorbatov ,  Guruprasad Settuvalli ,  Balaji Masanamuthu Chinnathurai ,  Sumant Tapas ,  Meghana Gudaram ,  Raj Kumar Subramaniam

IPC: G06F9/48 ,  G06F1/28 ,  G06F9/4401

Abstract: A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.

公开(公告)号：US20210349522A1

公开(公告)日：2021-11-11

申请号：US17215104

申请日：2021-03-29

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

IPC: G06F1/3296 ,  G06F1/3228 ,  G06F9/30

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

公开(公告)号：US20210208660A1

公开(公告)日：2021-07-08

申请号：US17210759

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/324 ,  G06F1/3296

Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US11029744B2

公开(公告)日：2021-06-08

申请号：US15857802

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Esfir Natanzon ,  Doron Rajwan ,  Eliezer Weissmann ,  Dorit Shapira ,  Lily P. Looi ,  Bart Plackle ,  Nadav Shulman

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/20 ,  G06F11/30 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3206

Abstract: In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.

公开(公告)号：US10963034B2

公开(公告)日：2021-03-30

申请号：US16546441

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3296

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.