公开(公告)号：US09767041B2

公开(公告)日：2017-09-19

申请号：US14721625

申请日：2015-05-26

Applicant: Intel Corporation

Inventor： Aravindh V. Anantaraman ,  Zvika Greenfield ,  Israel Diamand ,  Anant V. Nori ,  Pradeep Ramachandran ,  Nir Misgav

IPC: G06F12/12 ,  G06F12/08 ,  G06F12/121 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0893 ,  G06F12/0864 ,  G06F12/123 ,  G06F12/128 ,  G06F9/44

CPC classification number: G06F12/121 ,  G06F9/4418 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/608

Abstract: Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in the cache memory, perform a lookup operation for the first data element in the volatile memory and in response to a failed lookup operation, to generate a cache scrub hint forward the cache scrub hint to a cache scrub engine and identify one or more cache lines to scrub based at least in part on the cache scrub hint. Other examples are also disclosed and claimed.

公开(公告)号：US11543878B2

公开(公告)日：2023-01-03

申请号：US17042804

申请日：2018-05-01

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Eric Dehaemer ,  Alexander Gendler ,  Nadav Shulman ,  Krishnakanth Sistla ,  Nir Rosenzweig ,  Ankush Varma ,  Ariel Szapiro ,  Arye Albahari ,  Ido Melamed ,  Nir Misgav ,  Vivek Garg ,  Nimrod Angel ,  Adwait Purandare ,  Elkana Korem

IPC: G06F1/32 ,  G06F9/4401 ,  G06F1/329 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/48

Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

公开(公告)号：US20210200656A1

公开(公告)日：2021-07-01

申请号：US16728617

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： ELIEZER WEISSMANN ,  Omer Barak ,  Rajshree Chabukswar ,  Russell Fenger ,  Eugene Gorbatov ,  Monica Gupta ,  Julius Mandelblat ,  Nir Misgav ,  Efraim Rotem ,  Ahmad Yasin

IPC: G06F11/34 ,  G06F9/48 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

公开(公告)号：US11436118B2

公开(公告)日：2022-09-06

申请号：US16728617

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Omer Barak ,  Rajshree Chabukswar ,  Russell Fenger ,  Eugene Gorbatov ,  Monica Gupta ,  Julius Mandelblat ,  Nir Misgav ,  Efraim Rotem ,  Ahmad Yasin

IPC: G06F11/34 ,  G06F9/48 ,  G06F9/50 ,  G06F9/455 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

公开(公告)号：US20160350237A1

公开(公告)日：2016-12-01

申请号：US14721625

申请日：2015-05-26

Applicant: Intel Corporation

Inventor： Aravindh V. Anantaraman ,  Zvika Greenfield ,  Israel Diamand ,  Anant V. Nori ,  Pradeep Ramachandran ,  Nir Misgav

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/121 ,  G06F9/4418 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/608

Abstract: Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in the cache memory, perform a lookup operation for the first data element in the volatile memory and in response to a failed lookup operation, to generate a cache scrub hint forward the cache scrub hint to a cache scrub engine and identify one or more cache lines to scrub based at least in part on the cache scrub hint. Other examples are also disclosed and claimed.

Abstract translation: 描述了管理存储器操作的装置，系统和方法。 在一个示例中，控制器包括接收第一事务以对高速缓冲存储器中的第一数据元进行操作的逻辑，对易失性存储器中的第一数据元素执行查找操作，并响应于失败的查找操作，生成 缓存擦除提示将高速缓存擦除提示转发到缓存清理引擎，并至少部分基于缓存擦除提示来识别要擦除的一个或多个缓存行。 还公开并要求保护其他实例。

公开(公告)号：US20240231465A9

公开(公告)日：2024-07-11

申请号：US17969524

申请日：2022-10-19

Applicant: Intel Corporation

Inventor： Yoav Babajani ,  Hisham Abu Salah ,  Nadav Shulman ,  Nir Misgav ,  Arik Gihon

IPC: G06F1/324 ,  G06F1/3206

CPC classification number: G06F1/324 ,  G06F1/3206

Abstract: Embodiments herein relate to a technique to be performed by a power control unit (PCU) of an electronic device. Specifically, the PCU may identify, based on a metric related to an activity level of a processor core of a multi-core processor of the electronic device, first, second, and third weights that are respectively related to first, second, and third cores of the multi-core processor. Based on these weights, the PCU may identify a number of active processor cores of the multi-core processor, and alter a frequency limit of the multi-core processor accordingly. Other embodiments may be described and claimed.

公开(公告)号：US20240134440A1

公开(公告)日：2024-04-25

申请号：US17969524

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Yoav Babajani ,  Hisham Abu Salah ,  Nadav Shulman ,  Nir Misgav ,  Arik Gihon

IPC: G06F1/324 ,  G06F1/3206

CPC classification number: G06F1/324 ,  G06F1/3206

Abstract: Embodiments herein relate to a technique to be performed by a power control unit (PCU) of an electronic device. Specifically, the PCU may identify, based on a metric related to an activity level of a processor core of a multi-core processor of the electronic device, first, second, and third weights that are respectively related to first, second, and third cores of the multi-core processor. Based on these weights, the PCU may identify a number of active processor cores of the multi-core processor, and alter a frequency limit of the multi-core processor accordingly. Other embodiments may be described and claimed.

公开(公告)号：US10204047B2

公开(公告)日：2019-02-12

申请号：US14671892

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Nir Misgav ,  Aravindh Anantaraman ,  Zvika Greenfield

IPC: G06F12/0811

Abstract: An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.