公开(公告)号：US20220012115A1

公开(公告)日：2022-01-13

申请号：US17483713

申请日：2021-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Manoj Koul

IPC: G06F11/07 ,  G06K9/62 ,  G06T5/00 ,  G06K9/56 ,  G06K9/03

Abstract: Methods, apparatus, and articles of manufacture providing an efficient safety mechanism for signal processing hardware are disclosed. An example apparatus includes an input interface to receive an input signal; a hardware accelerator to process the input signal, the hardware accelerator including: unprotected memory to store non-critical data corresponding to the input signal; and protected memory to store critical data corresponding to the input signal; and an output interface to transmit the processed input signal.

公开(公告)号：US11157345B2

公开(公告)日：2021-10-26

申请号：US15844170

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Manoj Koul

IPC: G06F11/07 ,  G06K9/62 ,  G06T5/00 ,  G06K9/56 ,  G06K9/03 ,  G06T7/00 ,  H04L12/24

Abstract: Methods, apparatus, and articles of manufacture providing an efficient safety mechanism for signal processing hardware are disclosed. An example apparatus includes an input interface to receive an input signal; a hardware accelerator to process the input signal, the hardware accelerator including: unprotected memory to store non-critical data corresponding to the input signal; and protected memory to store critical data corresponding to the input signal; and an output interface to transmit the processed input signal.

公开(公告)号：US11144417B2

公开(公告)日：2021-10-12

申请号：US16236745

申请日：2018-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Mody ,  Gary Cooper ,  Anthony Lell

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/22 ,  G06F9/48 ,  G06F13/28 ,  G06F13/16

Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

公开(公告)号：US20210311782A1

公开(公告)日：2021-10-07

申请号：US17349310

申请日：2021-06-16

Applicant: Texas Instruments Incorporated

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, JR. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

公开(公告)号：US20210281862A1

公开(公告)日：2021-09-09

申请号：US17330840

申请日：2021-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/176 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/117

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

公开(公告)号：US11068308B2

公开(公告)日：2021-07-20

申请号：US16298709

申请日：2019-03-11

Applicant: Texas Instruments Incorporated

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, Jr. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

公开(公告)号：US20210103465A1

公开(公告)日：2021-04-08

申请号：US17123653

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48 ,  G06F9/50

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task sched

公开(公告)号：US20210049368A1

公开(公告)日：2021-02-18

申请号：US17086560

申请日：2020-11-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Anish Reghunath ,  Michael Peter Lachmayr

IPC: G06K9/00 ,  G06T7/20 ,  G06T1/00 ,  G06T7/269

Abstract: A computer vision system is provided that includes an image generation device configured to capture consecutive two dimensional (2D) images of a scene, a first memory configured to store the consecutive 2D images, a second memory configured to store a growing window of consecutive rows of a reference image and a growing window of consecutive rows of a current image, wherein the reference image and the current image are a pair of consecutive 2D images stored in the first memory, a third memory configured to store a sliding window of pixels fetched from the growing window of the reference image, wherein the pixels in the sliding window are stored in tiles, and a dense optical flow engine (DOFE) configured to determine a dense optical flow map for the pair of consecutive 2D images, wherein the DOFE uses the sliding window as a search window for pixel correspondence searches.

公开(公告)号：US20200349671A1

公开(公告)日：2020-11-05

申请号：US16930543

申请日：2020-07-16

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Brian Chae ,  Shashank Dabral ,  Niraj Nandan ,  Hetul Sanghvi

IPC: G06T3/40 ,  G06T1/20 ,  H04N1/393

Abstract: An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.

公开(公告)号：US10755380B2

公开(公告)日：2020-08-25

申请号：US15143491

申请日：2016-04-29

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Brian Chae ,  Shashank Dabral ,  Niraj Nandan ,  Hetul Sanghvi

IPC: G06K9/32 ,  G06T3/40 ,  G06T1/20 ,  H04N1/393

Abstract: An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.