公开(公告)号：US12204425B2

公开(公告)日：2025-01-21

申请号：US18243421

申请日：2023-09-07

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Mody ,  Gary Cooper ,  Anthony Lell

IPC: G06F11/00 ,  G06F9/48 ,  G06F11/22 ,  G06F11/273 ,  G06F13/16 ,  G06F13/28

Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

公开(公告)号：US11789836B2

公开(公告)日：2023-10-17

申请号：US17462046

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Mody ,  Gary Cooper ,  Anthony Lell

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/22 ,  G06F9/48 ,  G06F13/28 ,  G06F13/16

CPC classification number: G06F11/2733 ,  G06F9/4843 ,  G06F11/2242 ,  G06F13/1668 ,  G06F13/28

Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

公开(公告)号：US11144417B2

公开(公告)日：2021-10-12

申请号：US16236745

申请日：2018-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Mody ,  Gary Cooper ,  Anthony Lell

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/22 ,  G06F9/48 ,  G06F13/28 ,  G06F13/16

Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

公开(公告)号：US20200210301A1

公开(公告)日：2020-07-02

申请号：US16236745

申请日：2018-12-31

Applicant: Texas Instruments Incorporated

Inventor： NIRAJ NANDAN ,  Hetul Sanghvi ,  Mihir Mody ,  Gary Cooper ,  Anthony Lell

IPC: G06F11/273 ,  G06F11/22 ,  G06F13/16 ,  G06F13/28 ,  G06F9/48

Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.