公开(公告)号：US06595232B2

公开(公告)日：2003-07-22

申请号：US10163215

申请日：2002-06-04

Applicant: Guillaume Guzman ,  Jean-Pierre Themont

Inventor： Guillaume Guzman ,  Jean-Pierre Themont

IPC: F15C106

CPC classification number: B81C1/00119 ,  B01L3/5027 ,  B33Y70/00 ,  B33Y80/00 ,  B81B2201/058 ,  B81B2203/0353 ,  B81C1/00071 ,  B81C2201/019 ,  B81C2201/036 ,  C03B19/063 ,  C03B23/20 ,  Y10T137/0391 ,  Y10T137/0402 ,  Y10T137/2224 ,  Y10T137/6416

Abstract: The present invention relates to microfluidic devices and to their method of manufacture. The microfluidic devices are original by their specific structure (of sandwich type) and by the materials from which they are made (mainly glasses, glass ceramics, ceramics), and also by their specific method of manufacture, which is based on a vacuum-forming operation. The microfluidic device includes a first assembly including a microstructure and a first substrate, wherein the microstructure is constructed and arranged on the substrate under vacuum. A second assembly includes a second substrate positioned on the microstructure after the first assembly is presintered and adhered thereto by heat treatment to form a one-piece microstructure defining at least one recess between the first and second substrates.

公开(公告)号：US20030124837A1

公开(公告)日：2003-07-03

申请号：US10033032

申请日：2001-12-28

Inventor： Thomas Rueckes ,  Brent M. Segal ,  Darren K. Brock

IPC: H01L021/4763

CPC classification number: H01L21/76838 ,  B81C1/00142 ,  B81C2201/019 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  G11C2213/81 ,  H01H1/0094 ,  Y10S977/734

Abstract: Methods of producing an electromechanical circuit element are described. A lower structure having lower support structures and a lower electrically conductive element is provided. A nanotube ribbon (or other electromechanically responsive element) is formed on an upper surface of the lower structure so as to contact the lower support structures. An upper structure is provided over the nanotube ribbon. The upper structure includes upper support structures and an upper electrically conductive element. In some arrangements, the upper and lower electrically conductive elements are in vertical alignment, but in some arrangements they are not.

Abstract translation: 描述制造机电电路元件的方法。 提供具有较低支撑结构和较低导电元件的下部结构。 纳米管带（或其他机电响应元件）形成在下结构的上表面上以便接触下支撑结构。 在纳米管带上提供上部结构。 上部结构包括上部支撑结构和上部导电元件。 在一些布置中，上和下导电元件是垂直对准的，但在某些布置中它们不是。

公开(公告)号：US20030118277A1

公开(公告)日：2003-06-26

申请号：US10273628

申请日：2002-10-18

Applicant: Input/Output, Inc.

Inventor： Duli Yu ,  Arjun Selvakumar ,  Howard Goldberg ,  Taechung Yi

IPC: G02B006/26 ,  G02B006/42

CPC classification number: G02B26/0841 ,  B81B2201/047 ,  B81C1/00182 ,  B81C2201/019 ,  G02B6/3518 ,  G02B6/3548 ,  G02B6/357 ,  G02B2006/12104 ,  Y10S359/904

Abstract: The present invention provides a digital optical switch apparatus and process for manufacturing the apparatus. The apparatus includes a mirror assembly coupled to a top cap and to a bottom cap. The top and bottom caps each include one or more electrodes that, when energized with electrical energy, move a mirrored surface to one of a plurality of discrete positions. Mirror assemblies can be cascaded to create a packaged assembly having any multiple of discrete positions. The process includes planar micro-machining techniques to create isolated islands for electrical feed through. The process enables mechanical bonding of multiple tiers via a single bond region and through a bond-pad window.

Abstract translation: 本发明提供一种数字光开关装置及其制造方法。 该装置包括耦合到顶盖和底盖的反射镜组件。 顶盖和底盖各自包括一个或多个电极，当电能通电时，将镜面移动到多个离散位置中的一个。 镜子组件可以级联以创建具有任何多个离散位置的封装组件。 该过程包括平面微加工技术，以创建用于电子馈送的隔离岛。 该过程使得能够通过单键区域和键合焊盘窗口机械地结合多层。

公开(公告)号：US06569701B2

公开(公告)日：2003-05-27

申请号：US10002725

申请日：2001-10-25

Applicant: Michael J. Knieser ,  Robert J. Kretschmann ,  Mark A. Lucak ,  Richard D. Harris

Inventor： Michael J. Knieser ,  Robert J. Kretschmann ,  Mark A. Lucak ,  Richard D. Harris

IPC: H01L2100

CPC classification number: B81C1/00357 ,  B81C2201/019 ,  B81C2203/0109

Abstract: A method is presented for fabricating an electrically isolated MEMS device having a conductive outer MEMS element, and an inner movable MEMS element spaced apart from the conductive outer MEMS element. The inner element includes a nonconductive base having a plurality of conductive structures extending therefrom. The conductive components are formed by plating a conductive material into a pre-formed mold which defines the shape of the conductor.

Abstract translation: 提出了一种用于制造具有导电外部MEMS元件的电隔离MEMS器件的方法，以及与导电外部MEMS元件间隔开的内部可移动MEMS元件。 内部元件包括具有从其延伸的多个导电结构的非导电基底。 导电部件通过将导电材料镀覆到限定导体形状的预成型模具中而形成。

公开(公告)号：US20030082928A1

公开(公告)日：2003-05-01

申请号：US10002725

申请日：2001-10-25

Inventor： Michael J. Knieser ,  Robert J. Kretschmann ,  Mark A. Lucak ,  Richard D. Harris

IPC: H01L021/00 ,  C23F001/00

CPC classification number: B81C1/00357 ,  B81C2201/019 ,  B81C2203/0109

Abstract: A method is presented for fabricating an electrically isolated MEMS device having a conductive outer MEMS element, and an inner movable MEMS element spaced apart from the conductive outer MEMS element. The inner element includes a nonconductive base having a plurality of conductive structures extending therefrom. The conductive components are formed by plating a conductive material into a pre-formed mold which defines the shape of the conductor.

Abstract translation: 提出了一种用于制造具有导电外部MEMS元件的电隔离MEMS器件的方法，以及与导电外部MEMS元件间隔开的内部可移动MEMS元件。 内部元件包括具有从其延伸的多个导电结构的非导电基底。 导电部件通过将导电材料镀覆到限定导体形状的预成型模具中而形成。

公开(公告)号：US06555901B1

公开(公告)日：2003-04-29

申请号：US08943146

申请日：1997-10-03

Applicant: Shinji Yoshihara ,  Fumio Ohara ,  Masao Nagakubo

Inventor： Shinji Yoshihara ,  Fumio Ohara ,  Masao Nagakubo

IPC: H01L2306

CPC classification number: B81C1/00269 ,  B81C1/00357 ,  B81C1/00873 ,  B81C2201/019 ,  G01P15/0802 ,  G01P15/124 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16235 ,  H01L2924/00

Abstract: A sensing element is formed on a silicon (Si) substrate and covered with a cap. The cap has a leg portion having a titanium layer and a gold layer formed in that order on the lower surface thereof. The silicon substrate has an Si bonding frame at a position corresponding to the leg portion. When bonding the Si bonding frame of the silicon substrate and the leg portion of the cap, the titanium layer deoxidizes a naturally oxidized silicon layer formed on the Si bonding frame, whereby the silicon substrate and the cap can be uniformly bonded together with an Au/Si eutectic portion interposed therebetween. In this case, the Au/Si eutectic portion includes a titanium oxide accompanying the deoxidization of the naturally oxidized silicon layer.

Abstract translation: 感测元件形成在硅（Si）衬底上并被盖覆盖。 盖具有在其下表面上依次形成钛层和金层的腿部。 硅衬底在对应于腿部的位置处具有Si接合框架。 当结合硅基板的Si接合框架和盖的腿部时，钛层对形成在Si接合框架上的自然氧化的硅层进行脱氧，从而可以将硅基板和盖子与Au / Si共晶部分插入其间。 在这种情况下，Au / Si共晶部分包括伴随着氧化硅层的脱氧的氧化钛。

公开(公告)号：US06518084B1

公开(公告)日：2003-02-11

申请号：US09868402

申请日：2001-09-12

Applicant: Stefan Seitz ,  Leonhard Hoefter ,  Juergen Kruckow ,  Karl Neumeier ,  Dieter Bollmann

Inventor： Stefan Seitz ,  Leonhard Hoefter ,  Juergen Kruckow ,  Karl Neumeier ,  Dieter Bollmann

IPC: H01L2100

CPC classification number: G01P15/0802 ,  B81B2203/0127 ,  B81C1/00246 ,  B81C2201/019 ,  B81C2203/0728 ,  G01L9/0042 ,  G01L9/0073

Abstract: In a method of producing a micromechanical structure for a micro-electromechanical element, a first intermediate layer, which is applied to a first main surface of a first semiconductor wafer, is structured in a first step so as to produce a recess. The first semiconductor wafer is then connected via the first intermediate layer to a second semiconductor wafer in such a way that a hermetically sealed cavity is defined by the recess. Finally, one of the wafers is thinned from a surface facing away from said first intermediate layer so as to produce a diaphragm-like structure on top of the cavity. At least one further intermediate layer is provided between the two semiconductor wavers which, prior to the connection of the two semiconductor wafers, is structured in such a way that the structure formed in said at least one further intermediate layer and the recess in said first intermediate layer define the cavity.

Abstract translation: 在制造微电子机电元件的微机械结构的方法中，施加到第一半导体晶片的第一主表面的第一中间层被构造成第一步骤以产生凹陷。 然后将第一半导体晶片经由第一中间层连接到第二半导体晶片，使得由凹部限定气密密封腔。 最后，其中一个晶片从背离所述第一中间层的表面变薄，从而在空腔的顶部产生隔膜状结构。 在两个半导体波幅之间提供至少一个另外的中间层，其在两个半导体晶片的连接之前被构造成使得在所述至少一个另外的中间层中形成的结构和所述第一中间层 层定义空腔。

公开(公告)号：US20030020062A1

公开(公告)日：2003-01-30

申请号：US10222439

申请日：2002-08-15

Inventor： Sadeg M. Faris

IPC: H01L035/24

CPC classification number: B81C1/00238 ,  B81C1/0038 ,  B81C2201/019 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to micro electro-mechanical systems (MEMS) and production methods thereof, and more particularly to vertically integrated MEMS systems. Manufacturing of MEMS and vertically integrated MEMS is facilitated by forming, preferably on a wafer level, plural MEMS on a MEMS layer selectively bonded to a substrate, and removing the MEMS layer intact.

Abstract translation: 本发明涉及微机电系统（MEMS）及其制造方法，更具体地涉及垂直集成的MEMS系统。 MEMS和垂直集成MEMS的制造通过优选在晶片级上在选择性地结合到衬底的MEMS层上形成多个MEMS并且完整地去除MEMS层来促进。

公开(公告)号：US06498053B2

公开(公告)日：2002-12-24

申请号：US10153473

申请日：2002-05-21

Applicant: Ubaldo Mastromatteo ,  Fabrizio Ghironi ,  Roberto Aina ,  Mauro Bombonati

Inventor： Ubaldo Mastromatteo ,  Fabrizio Ghironi ,  Roberto Aina ,  Mauro Bombonati

IPC: H01L2144

CPC classification number: B81C1/00238 ,  B81C2201/019 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01322

Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.

公开(公告)号：US20020174935A1

公开(公告)日：2002-11-28

申请号：US09865330

申请日：2001-05-25

Applicant: Motorola, Inc.

Inventor： Jeremy W. Burdon ,  David L. Wilcox

IPC: C03B029/00

CPC classification number: B32B18/00 ,  B32B2311/04 ,  B32B2311/08 ,  B32B2311/09 ,  B32B2315/02 ,  B81B2201/058 ,  B81C1/00119 ,  B81C2201/019 ,  C04B35/111 ,  C04B35/486 ,  C04B35/565 ,  C04B35/581 ,  C04B35/584 ,  C04B35/634 ,  C04B35/63424 ,  C04B35/638 ,  C04B2235/36 ,  C04B2235/365 ,  C04B2235/656 ,  C04B2237/32 ,  C04B2237/343 ,  C04B2237/348 ,  C04B2237/365 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/52 ,  C04B2237/561 ,  C04B2237/62 ,  C04B2237/68 ,  C04B2237/704 ,  G03F7/0017 ,  H05K1/0306 ,  H05K3/0014 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/0759

Abstract: Cast-on-resist (COR) methods of manufacturing patterned ceramic layers that can be used in forming a multilayered ceramic device are provided according to preferred exemplary embodiments of the present invention. The COR methods are comprised of processing steps that are conducted on a transporting system and include: depositing a resist on a substrate (102) and selectively exposing the resist to a radiation source (104) such that a first portion of the resist having a positive image of the pattern is soluble in a solvent and a second portion of the resist having a negative image of the pattern is insoluble in the solvent, immersing the resist in the solvent to remove the first portion to form a casting substrate having the negative image of the pattern (106), applying ceramic slurry on the casting substrate (204), curing the ceramic slurry on the casting substrate (206), and removing the ceramic slurry from the casting substrate after the curing such that a patterned ceramic layer is formed for use in a multilayered ceramic device (208).

Abstract translation: 根据本发明的优选示例性实施例提供了可用于形成多层陶瓷器件的图案化陶瓷层的抗蚀刻（COR）抗蚀剂（COR）方法。 COR方法包括在传送系统上进行的处理步骤，包括：在衬底（102）上沉积抗蚀剂并选择性地将抗蚀剂暴露于辐射源（104），使得抗蚀剂的第一部分具有阳性 图案的图像可溶于溶剂，具有图案的负像的抗蚀剂的第二部分不溶于溶剂中，将抗蚀剂浸入溶剂中以除去第一部分以形成具有负像的 图案（106），在铸造基材（204）上施加陶瓷浆料，固化铸塑基材（206）上的陶瓷浆料，以及在固化之后从铸造基材除去陶瓷浆料，使得形成图案化的陶瓷层， 用于多层陶瓷器件（208）中。