公开(公告)号：US20240246812A1

公开(公告)日：2024-07-25

申请号：US18564996

申请日：2022-06-22

Applicant: UNIVERSITY OF WASHINGTON

Inventor： Bo Zhang ,  Todd Anderson ,  Chris McAllister

IPC: B81C1/00 ,  B81B7/00 ,  C03C15/00 ,  C03C17/22 ,  C03C17/245 ,  C23C16/02 ,  C23C16/34 ,  C23C16/40 ,  C23C16/50 ,  C23C16/56 ,  G01N33/487

CPC classification number: B81C1/00341 ,  B81B7/00 ,  C03C15/00 ,  C03C17/225 ,  C03C17/245 ,  C23C16/0227 ,  C23C16/345 ,  C23C16/401 ,  C23C16/50 ,  C23C16/56 ,  G01N33/48721 ,  B81B2203/0127 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0176 ,  B81C2201/019 ,  C03C2218/152 ,  C03C2218/153 ,  C03C2218/32

Abstract: An ultrathin free-standing solid state membrane, including an etched well on a glass wafer, and a layer of SiX deposited on a backside of the etched well on the glass wafer.

公开(公告)号：US20240017989A1

公开(公告)日：2024-01-18

申请号：US18348664

申请日：2023-07-07

Applicant: ROHM CO., LTD.

Inventor： Martin Wilfried HELLER

IPC: B81C1/00 ,  B81B7/02

CPC classification number: B81C1/00166 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81B2203/033 ,  B81B2203/04 ,  B81C2201/0132 ,  B81C2201/0177 ,  B81C2201/019 ,  B81C2201/0178

Abstract: A MEMS device includes a substrate which has a first main surface and a second main surface facing the first main surface, and in which a silicon substrate, a silicon carbide layer having conductivity, and a silicon layer are sequentially stacked from a second main surface side toward a first main surface side, a cavity recessed over the silicon layer, the silicon carbide layer, and the silicon substrate from the first main surface of the substrate to the second main surface side of the substrate, a MEMS electrode which is arranged in the cavity, is composed of the silicon layer and the silicon carbide layer, and is spaced apart from a bottom surface of the cavity to the first main surface side, and an isolation joint which divides the MEMS electrode in a plan view and mechanically connects and electrically isolates both sides of the divided MEMS electrode.

公开(公告)号：US11828729B2

公开(公告)日：2023-11-28

申请号：US16986067

申请日：2020-08-05

Applicant: BFLY OPERATIONS, INC.

Inventor： Jonathan M. Rothberg ,  Susan A. Alie ,  Keith G. Fife ,  Nevada J. Sanchez ,  Tyler S. Ralston

IPC: G01N29/24 ,  B81C1/00 ,  B06B1/02 ,  A61B8/00 ,  B81B7/00

CPC classification number: G01N29/2406 ,  A61B8/4483 ,  B06B1/0292 ,  B81B7/007 ,  B81C1/00238 ,  B81C1/00301 ,  B81B2201/0271 ,  B81C2201/019 ,  B81C2203/036 ,  B81C2203/0792 ,  H01L2224/4813 ,  H01L2924/0002 ,  H01L2924/146 ,  H01L2924/1461

Abstract: Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

公开(公告)号：US11713241B2

公开(公告)日：2023-08-01

申请号：US17444212

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Chih-Ming Chen ,  Yuan-Chih Hsieh ,  Chung-Yi Yu

IPC: B81B7/00 ,  B81C1/00 ,  H01L23/488 ,  H01L25/00 ,  H01L23/00

CPC classification number: B81C1/00269 ,  B81B7/0041 ,  B81C1/00 ,  B81C1/00238 ,  H01L23/488 ,  H01L25/50 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2207/012 ,  B81B2207/093 ,  B81C2201/019 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/035 ,  B81C2203/036 ,  H01L24/02 ,  H01L24/06 ,  H01L24/81

Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

公开(公告)号：US11649159B2

公开(公告)日：2023-05-16

申请号：US17020702

申请日：2020-09-14

Applicant: The Government of the United States of America, as represented by the Secretary of the Navy

Inventor： Francis J. Kub ,  Karl D. Hobart ,  Eugene A. Imhoff ,  Rachael L. Myers-Ward

IPC: B81B3/00 ,  B81C1/00 ,  H01L29/16

CPC classification number: B81B3/0021 ,  B81B3/0072 ,  B81C1/00531 ,  H01L29/1608 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2203/0127 ,  B81C2201/019

Abstract: A method of fabricating suspended beam silicon carbide microelectromechanical (MEMS) structure with low capacitance and good thermal expansion match. A suspended material structure is attached to an anchor material structure that is direct wafer bonded to a substrate. The anchor material structure and the suspended material structure are formed from either a hexagonal single-crystal SiC material, and the anchor material structure is bonded to the substrate while the suspended material structure does not have to be attached to the substrate. The substrate may be a semi-insulating or insulating SiC substrate. The substrate may have an etched recess region on the substrate first surface to facilitate the formation of the movable suspended material structures. The substrate may have patterned electrical electrodes on the substrate first surface, within recesses etched into the substrate.

公开(公告)号：US20190233280A1

公开(公告)日：2019-08-01

申请号：US16213019

申请日：2018-12-07

Applicant: Shenyang Silicon Technology Co., Ltd.

Inventor： Xiang LI

IPC: B81C1/00 ,  B81B1/00

CPC classification number: B81C1/00047 ,  B08B3/08 ,  B32B37/06 ,  B32B38/0008 ,  B32B43/006 ,  B32B2038/0016 ,  B32B2310/14 ,  B32B2313/00 ,  B32B2457/14 ,  B81B1/004 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C1/00357 ,  B81C1/00507 ,  B81C1/00849 ,  B81C2201/0116 ,  B81C2201/0125 ,  B81C2201/0178 ,  B81C2201/019 ,  B81C2201/0192 ,  B81C2201/0194

Abstract: A method for processing a silicon wafer with a through cavity structure. The method is operated in accordance with the following sequence: performing ion implantation on a silicon wafer or pattern wafer; implanting a dummy substrate; bonding the silicon wafer to the pattern wafer; performing grinding and polishing, and thinning the pattern wafer to a depth exposing the pattern; bonding; and peeling the dummy substrate. Compared with the prior art, the present invention is standard in operation, and the product quality can be effectively guaranteed. The product has high cost performance and excellent comprehensive technical effect. The present invention has expectable relatively large economic values and social values.

公开(公告)号：US20190104616A1

公开(公告)日：2019-04-04

申请号：US16143677

申请日：2018-09-27

Applicant: Stephen A. Marsh

Inventor： Stephen A. Marsh

IPC: H05K1/18 ,  B81C1/00 ,  B81B3/00 ,  H05K1/03

CPC classification number: H05K1/189 ,  B81B3/0021 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2201/0292 ,  B81C1/0015 ,  B81C1/00166 ,  B81C99/0095 ,  B81C2201/019 ,  B81C2203/038 ,  B81C2203/051 ,  G01P15/125 ,  H05K1/0393

Abstract: Disclosed is a flexible electronic circuit substrate that includes a device that is fabricated from layers of the flexible electronic circuit substrate as part of construction of the flexible electronic circuit substrate. Such devices could be functional units such as micro electro mechanical devices (MEMS) devices such as micro-accelerometer sensor elements, micro flow sensors, micro pressure sensors, etc.

公开(公告)号：US20180215611A1

公开(公告)日：2018-08-02

申请号：US15937398

申请日：2018-03-27

Applicant: VAON, LLC

Inventor： Henry Steen ,  Alexander Larin ,  Jon Paschal ,  Quentin Lineberry ,  Keith Andrew ,  Phillip Womble

IPC: B81B7/00 ,  B32B3/26 ,  B32B17/06 ,  B81B5/00

CPC classification number: B81B7/0058 ,  B32B3/266 ,  B32B17/06 ,  B32B2457/00 ,  B81B3/0081 ,  B81B5/00 ,  B81B2201/0214 ,  B81B2203/056 ,  B81B2203/06 ,  B81C1/00182 ,  B81C2201/019

Abstract: The present invention generally relates to multi-layer glass structures and methods of making the same.

公开(公告)号：US10035701B2

公开(公告)日：2018-07-31

申请号：US15305799

申请日：2014-11-05

Applicant: ADVANCED SEMICONDUCTOR MANUFACTURING CO. LTD

Inventor： Yuanjun Xu ,  Yilin Yan ,  Weijia Xue

IPC: B81B7/02 ,  B81C1/00

CPC classification number: B81B7/02 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00158 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/019 ,  B81C2201/0198 ,  B81C2201/053

Abstract: There is provided a method for forming a composite cavity and a composite cavity formed using the method. The method comprises the following steps: providing a silicon substrate (101); forming an oxide layer on the front side thereof; patterning the oxide layer to form one or more grooves (103), the position of the groove (103) corresponding to the position of small cavity (109) to be formed; providing a bonding wafer (104), which is bonded to the patterned oxide layer to form one or more closed micro-cavity structures (105) between the silicon substrate (101) and the bonding wafer (104); forming a protective film (106) over the bonding wafer (104) and forming a masking layer (107) on the back side of the silicon substrate (101); patterning the masking layer (107), the pattern of the masking layer (107) corresponding to the position of a large cavity (108) to be formed; using the masking layer (107) as a mask, etching the silicon substrate (101) from the back side until the oxide layer at the front side thereof to form the large cavity (108) in the silicon substrate (101); and using the masking layer (107) and the oxide layer as a mask, etching the bonding wafer (104) from the back side through the silicon substrate (101) until the protective film (106) thereover to form one or more small cavities (109) in the bonding wafer (104). The uniformity of thickness of the semiconductor medium layer where the small cavity (109) in the composite cavity is located is well controlled by the present invention.

公开(公告)号：US10017378B2

公开(公告)日：2018-07-10

申请号：US15265434

申请日：2016-09-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wen Cheng ,  Chia-Hua Chu

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C1/00238 ,  B81C1/00301 ,  B81C2201/019 ,  B81C2203/0792

Abstract: A method embodiment includes providing a MEMS wafer. A portion of the MEMS wafer is patterned to provide a first membrane for a microphone device and a second membrane for a pressure sensor device. A carrier wafer is bonded to the MEMS wafer. The carrier wafer is etched to expose the first membrane and a first surface of the second membrane to an ambient environment. A MEMS structure is formed in the MEMS wafer. A cap wafer is bonded to a side of the MEMS wafer opposing the carrier wafer to form a first sealed cavity including the MEMS structure and a second sealed cavity including a second surface of the second membrane for the pressure sensor device. The cap wafer comprises an interconnect structure. A through-via electrically connected to the interconnect structure is formed in the cap wafer.