公开(公告)号：US20180089129A1

公开(公告)日：2018-03-29

申请号：US15696747

申请日：2017-09-06

Applicant: Jonathan Glickman

Inventor： Jonathan Glickman

IPC: G06F13/40 ,  G06F13/42 ,  G06F12/02 ,  G06F13/28 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F12/0246 ,  G06F13/1694 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/7201

Abstract: A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.

公开(公告)号：US20180088812A1

公开(公告)日：2018-03-29

申请号：US15497258

申请日：2017-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Pyung Lee

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1041 ,  G06F2212/7201 ,  Y02D10/154

Abstract: A method of operating a storage device including at least one nonvolatile storage and a storage controller configured to control the nonvolatile storage. A first type of request, original data and a first request information associated with the original data are received, in the storage controller, from an external host device, a compression operation to compress the original data to generate compressed data is performed in the storage controller, in response to the first type of request, and a write operation to write the compressed data in a data storage area of the nonvolatile storage is performed in the storage controller. The data storage area of the nonvolatile storage may store the first request information associated with the original data. The external host may manage mapping information in the form of a mapping table associated with compression/decompression at the storage device.

公开(公告)号：US20180088811A1

公开(公告)日：2018-03-29

申请号：US15446796

申请日：2017-03-01

Applicant: Toshiba Memory Corporation

Inventor： Shinichi KANNO

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/0608 ,  G06F3/0638 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A storage device includes a nonvolatile storage and a controller. The controller is configured to compress data received from a host in association with a write command designating a first data length as a length of the data and a starting logical address of the data, into compressed data of a second data length shorter than the first data length, write the compressed data in the nonvolatile storage. Further, the controller is configured to generate an address mapping for the data, such that a first logical address range that starts at the starting logical address is mapped to a physical region of the nonvolatile storage having a size equal to the second data length, and a second logical address range that directly follows the first logical address range is not mapped to any physical region of the nonvolatile storage.

公开(公告)号：US09928169B2

公开(公告)日：2018-03-27

申请号：US14272238

申请日：2014-05-07

Applicant: SanDisk Technologies Inc.

Inventor： Leon Romanovsky ,  Alon Marcu

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/08 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F12/08 ,  G06F3/061 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2206/1014 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7205 ,  Y02D10/13

Abstract: A method and system for improving swap performance are provided. In one embodiment, a computing device is provided with a volatile memory and a non-volatile memory, wherein the non-volatile memory has a first swap area with multi-level cell (MLC) memory and a second swap area with single-level cell (SLC) memory. One of the characteristics of SLC memory is that data is written more quickly in the SLC memory than the MLC memory. A determination is made whether the computing device is operating in normal mode or burst mode. If it is determined that the computing device is operating in normal mode, data is moved from the volatile memory to the first swap area during a swap operation. If it is determined that the computing device is operating in burst mode, data is moved from the volatile memory to the second swap area during a swap operation.

公开(公告)号：US09921957B2

公开(公告)日：2018-03-20

申请号：US15682283

申请日：2017-08-21

Applicant: Facebook, Inc.

Inventor： Dung Nguyen Tien ,  Fraidun Akhi ,  Jonathan Cook

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F12/0638 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: A method is performed at an electronic device with a display, one or more processors, volatile memory, and non-volatile memory that stores one or more programs for execution by the one or more processors. The method includes periodically comparing an amount of free volatile memory to a threshold level. The amount of free volatile memory is compared to the threshold level with a first periodicity when the display is off and with a second periodicity that is shorter than the first periodicity when the display is on. The method also includes, in response to a determination that the amount of free volatile memory does not satisfy the threshold level, deallocating volatile memory by terminating one or more processes based on priority levels of the one or more processes.

公开(公告)号：US20180074722A1

公开(公告)日：2018-03-15

申请号：US15453016

申请日：2017-03-08

Applicant: Toshiba Memory Corporation

Inventor： Daisuke IWAI

IPC: G06F3/06 ,  G06F12/1018

CPC classification number: G06F3/0611 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/1433 ,  G06F21/00 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/1052 ,  G06F2212/7201 ,  Y02D10/13

Abstract: According to one embodiment, a storage device includes a nonvolatile memory storing first data, and a device controller which is capable of storing all or a part of the first data stored in the nonvolatile memory as second data to a memory area in a host. The device controller which is configured to calculate a first hash value of the second data stored in the memory area in a first timing, calculate a second hash value of the second data stored in the memory area in a second timing, and detect whether the second data stored in the memory area is tampered between the first and second timings by comparing the second hash value with the first hash value.

公开(公告)号：US09916260B2

公开(公告)日：2018-03-13

申请号：US14929174

申请日：2015-10-30

Applicant: Microsoft Technology Licensing, LLC

Inventor： Landy Wang

IPC: G06F12/00 ,  G06F12/123 ,  G06F12/12 ,  G06F12/02 ,  G06F12/06 ,  G06F12/1009 ,  G06F3/06

CPC classification number: G06F12/123 ,  G06F3/06 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/1009 ,  G06F12/12 ,  G06F2212/202 ,  G06F2212/2028 ,  G06F2212/65 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: A memory manager in a computer system that ages memory for high performance. The efficiency of operation of the computer system can be improved by dynamically setting an aging schedule based on a predicted time for trimming pages from a working set. An aging schedule that generates aging information that better discriminates among pages in a working set based on activity level enables selection of pages to trim that are less likely to be accessed following trimming. As a result of being able to identify and trim less active pages, inefficiencies arising from restoring trimmed pages to the working set are avoided.

公开(公告)号：US20180067692A1

公开(公告)日：2018-03-08

申请号：US15499444

申请日：2017-04-27

Applicant: SK hynix Inc.

Inventor： Ik-Sung OH

IPC: G06F3/06 ,  G06F12/12

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0626 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/7201

Abstract: A controller may include a first map buffer and a second map buffer suitable for storing map data and hit counts respectively corresponding to the map data, wherein each of the hit counts represents a number of accesses to data stored in a memory device by using a corresponding one among the map data, and wherein the controller swaps the map data and corresponding hit counts between the first and second map buffers such that the first map buffer stores relatively higher hit counts and corresponding map data than the second map buffer.

公开(公告)号：US09910602B2

公开(公告)日：2018-03-06

申请号：US15270197

申请日：2016-09-20

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hideki Yoshida ,  Tatsunori Kanai ,  Masaya Tarui ,  Yutaka Yamada

IPC: G06F3/06 ,  G06F12/123 ,  G06F12/0808 ,  G06F12/06 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/12 ,  G06F12/02 ,  G06F12/0811 ,  G11C7/10 ,  G06F12/0868

CPC classification number: G06F3/061 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/1009 ,  G06F12/12 ,  G06F12/123 ,  G06F2212/283 ,  G06F2212/651 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C7/1072

Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.

公开(公告)号：US09910597B2

公开(公告)日：2018-03-06

申请号：US15391184

申请日：2016-12-27

Applicant: Toshiba Memory Corporation

Inventor： Hiroshi Yao ,  Shinichi Kanno ,  Kazuhiro Fukutomi

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/0634 ,  G06F3/0641 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.