公开(公告)号：US10032647B2

公开(公告)日：2018-07-24

申请号：US15587930

申请日：2017-05-05

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L23/48 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/49827 ,  H01L24/43 ,  H01L24/46 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/023 ,  H01L2224/4502 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.

公开(公告)号：US20180096960A1

公开(公告)日：2018-04-05

申请号：US15831231

申请日：2017-12-04

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/00 ,  H05K3/34 ,  H01L25/00 ,  H01L25/065 ,  H01L21/683

CPC classification number: H01L24/17 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/034 ,  H01L2224/03612 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1012 ,  H01L2224/10155 ,  H01L2224/11003 ,  H01L2224/11013 ,  H01L2224/111 ,  H01L2224/1111 ,  H01L2224/1112 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/11438 ,  H01L2224/1144 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/1161 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11912 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13187 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/381 ,  H05K3/3436 ,  H05K3/3478 ,  H05K2203/0415 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

公开(公告)号：US20180082916A1

公开(公告)日：2018-03-22

申请号：US15827550

申请日：2017-11-30

Applicant: Invensas Corporation

Inventor： Rajesh Katkar

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L23/3107 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/10 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83005 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a plurality of microelectronic element attachment regions on a carrier. The attachment regions being spaced apart from one another and overlying the carrier. The method also including the formation of conductive connector elements between adjacent attachment regions. Each connector element having the first or second end adjacent the carrier and the remaining end at a height of the microelectronic element. The method also includes forming an encapsulation over portions of the connector elements and subsequently singulating the assembly. into microelectronic units, each including a microelectronic element. The surface of the microelectronic unit, opposite the redistribution structure, having both the active face of the microelectronic element and the free ends of the connector elements so that both are available for connection with a component external to the microelectronic unit.

公开(公告)号：US09899442B2

公开(公告)日：2018-02-20

申请号：US14945292

申请日：2015-11-18

Applicant: Invensas Corporation

Inventor： Rajesh Katkar

IPC: H01L31/062 ,  H01L27/146 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L27/14634 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/18 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2924/15153

Abstract: An image sensor device, as well as methods therefor, is disclosed. This image sensor device includes a substrate having bond pads. The substrate has a through substrate channel defined therein extending between a front side surface and a back side surface thereof. The front side surface is associated with an optically-activatable surface. The bond pads are located at or proximal to the front side surface aligned for access via the through substrate channel. Wire bond wires are bonded to the bond pads at first ends thereof extending away from the bond pads with second ends of the wire bond wires located outside of an opening of the channel at the back side surface. A molding layer is disposed along the back side surface and in the through substrate channel. A redistribution layer is in contact with the molding layer and interconnected to the second ends of the wire bond wires.

公开(公告)号：US20180019191A1

公开(公告)日：2018-01-18

申请号：US15715515

申请日：2017-09-26

Applicant: INVENSAS CORPORATION

Inventor： Cyprian Emeka UZOH ,  Rajesh Katkar

IPC: H01L23/498 ,  B23K1/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  B32B15/01 ,  B23K35/22 ,  B23K35/02 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  B23K101/40

CPC classification number: H01L23/49811 ,  B23K1/0016 ,  B23K35/0244 ,  B23K35/0266 ,  B23K35/22 ,  B23K2101/40 ,  B32B15/01 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/98 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/03001 ,  H01L2224/03009 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/0333 ,  H01L2224/03334 ,  H01L2224/0348 ,  H01L2224/03848 ,  H01L2224/03849 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/0391 ,  H01L2224/04105 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05294 ,  H01L2224/05547 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/056 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/05844 ,  H01L2224/05847 ,  H01L2224/05855 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/10145 ,  H01L2224/11001 ,  H01L2224/11005 ,  H01L2224/11009 ,  H01L2224/111 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/2401 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/75253 ,  H01L2224/81 ,  H01L2224/81138 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8122 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/82105 ,  H01L2224/83 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841

Abstract: A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.

公开(公告)号：US09859257B2

公开(公告)日：2018-01-02

申请号：US15358380

申请日：2016-11-22

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Tu Tam Vu ,  Rajesh Katkar

IPC: H01L23/495 ,  H01L21/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49051 ,  H01L2224/4909 ,  H01L2224/49113 ,  H01L2224/49173 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/06 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: Stacked microelectronic packages comprise microelectronic elements each having a contact-bearing front surface and edge surfaces extending away therefrom, and a dielectric encapsulation region contacting an edge surface. The encapsulation defines first and second major surfaces of the package and a remote surface between the major surfaces. Package contacts at the remote surface include a first set of contacts at positions closer to the first major surface than a second set of contacts, which instead are at positions closer to the second major surface. The packages are configured such that major surfaces of each package can be oriented in a nonparallel direction with the major surface of a substrate, the package contacts electrically coupled to corresponding contacts at the substrate surface. The package stacking and orientation can provide increased packing density.

公开(公告)号：US09842819B2

公开(公告)日：2017-12-12

申请号：US14832996

申请日：2015-08-21

Applicant: INVENSAS CORPORATION

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/034 ,  H01L2224/03612 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1012 ,  H01L2224/10155 ,  H01L2224/11003 ,  H01L2224/11013 ,  H01L2224/111 ,  H01L2224/1111 ,  H01L2224/1112 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/11438 ,  H01L2224/1144 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/1161 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11912 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13187 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/381 ,  H05K3/3436 ,  H05K3/3478 ,  H05K2203/0415 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

公开(公告)号：US09831302B2

公开(公告)日：2017-11-28

申请号：US15360121

申请日：2016-11-23

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L21/02 ,  H01L49/02 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/11 ,  H01L25/16 ,  H01L25/00 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

公开(公告)号：US09761517B2

公开(公告)日：2017-09-12

申请号：US15477265

申请日：2017-04-03

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H05K1/09 ,  H05K1/00 ,  H05K1/11 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/373 ,  H01L21/48

CPC classification number: H05K1/0306 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3731 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/09 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0323

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

公开(公告)号：US09754866B2

公开(公告)日：2017-09-05

申请号：US15248726

申请日：2016-08-26

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen ,  Cyprian Emeka Uzoh ,  Belgacem Haba

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L25/10 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L23/04 ,  H01L25/00

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/1427 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2224/81

Abstract: A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.