公开(公告)号：US09983880B2

公开(公告)日：2018-05-29

申请号：US14497974

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Rekai Gonzalez-Alberquilla ,  Tanausu Ramirez ,  Josep M. Codina ,  Enric Gibert Codina

IPC: G06F9/38 ,  G06F9/48 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1036

CPC classification number: G06F9/3851 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3867 ,  G06F9/4881 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/68 ,  G06F2212/684

Abstract: An apparatus and method are described for improved thread selection. For example, one embodiment of a processor comprises: first logic to maintain a history table comprising a plurality of entries, each entry in the table associated with an instruction and including history data indicating prior hits and/or misses to a cache level and/or a translation lookaside buffer (TLB) for that instruction; and second logic to select a particular thread for execution at a particular processor pipeline stage based on the history data.

公开(公告)号：US09940259B2

公开(公告)日：2018-04-10

申请号：US14598872

申请日：2015-01-16

Applicant: International Business Machines Corporation

Inventor： Nathan D. Fontenot ,  Robert C. Jennings, Jr. ,  Joel H. Schopp ,  Michael T. Strosaker

IPC: G06F12/10 ,  G06F12/1036

CPC classification number: G06F12/10 ,  G06F3/06 ,  G06F12/1036 ,  G06F2212/152 ,  G06F2212/657

Abstract: Embodiments relate to a virtualized storage environment with one or more virtual machines operating on a host and sharing host resources. Each virtual machine has a virtual disk in communication with a persistent storage device. The virtual machine(s) may be misaligned with the persistent storage device so that a virtual block address does not correspond with a persistent storage block address. A relationship between the virtual disk(s) and the persistent storage device is established, and more specifically, an alignment delta between the devices is established. The delta is employed to translate the virtual address to the persistent address so that the virtual and persistent storage blocks are aligned to satisfy a read or write operation.

公开(公告)号：US09934159B2

公开(公告)日：2018-04-03

申请号：US15159938

申请日：2016-05-20

Applicant: International Business Machines Corporation

Inventor： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/02 ,  G06F12/1036 ,  G06F9/30 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F12/0215 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/145 ,  G06F2212/1052 ,  G06F2212/654 ,  G06F2212/656 ,  G06F2212/68

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.

公开(公告)号：US20170344488A1

公开(公告)日：2017-11-30

申请号：US15682259

申请日：2017-08-21

Applicant: Oracle Corporation

Inventor： ULADZISLAU SHARANHOVICH ,  Anand Srinivasan ,  Dmitry Golovashkin ,  Vaishnavi Sashikanth

IPC: G06F12/10 ,  G06F12/1018 ,  G06F9/54 ,  G06F12/1036 ,  G06F17/30

CPC classification number: G06F12/10 ,  G06F9/544 ,  G06F12/1018 ,  G06F12/1036 ,  G06F17/3015 ,  G06F2212/657

Abstract: Techniques herein are for sharing data structures. In embodiments, a computer obtains a directed object graph (DOG) containing objects and pointers interconnecting the objects. Each object pointer (OP) resides in a source object and comprises a memory address (MA) of a target object (TO). An original address space (OAS) contains the MA of the TO. The objects are not contiguous within the OAS. The DOG resides in original memory segment(s). The computer obtains an additional memory segment (AMS) beginning at a base address. The computer records the base address within the AMS. For each object in the DOG, the computer copies the object into the AMS at a respective address. For each OP in the DOG having the object as the TO of the MA of the OP, the computer replaces the MA of the OP with the respective address. AMS contents are provided in another address space.

公开(公告)号：US09811472B2

公开(公告)日：2017-11-07

申请号：US13517758

申请日：2012-06-14

Applicant: Anthony J. Bybell ,  Michael K. Gschwind

Inventor： Anthony J. Bybell ,  Michael K. Gschwind

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1027 ,  G06F12/1018

CPC classification number: G06F12/1009 ,  G06F12/1018 ,  G06F12/1027 ,  G06F12/1036

Abstract: Embodiments relate to managing memory page tables in a processing system. A request to access a desired block of memory is received. The request includes an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address including a most significant portion and a byte index. An entry in a buffer that includes the ESID of the effective address is located. Based on the entry including a radix page table pointer (RPTP), performing: using the RPTP to locate a translation table of a hierarchy of translation tables, using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory, and based on the obtained address, performing the requested access to the desired block of memory.

公开(公告)号：US09785569B2

公开(公告)日：2017-10-10

申请号：US13785188

申请日：2013-03-05

Applicant: International Business Machines Corporation

Inventor： Anthony J. Bybell ,  Michael K. Gschwind

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1027 ,  G06F12/1018

CPC classification number: G06F12/1009 ,  G06F12/1018 ,  G06F12/1027 ,  G06F12/1036

Abstract: A method includes receiving a request to access a desired block of memory. The request includes an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address comprising a most significant portion and a byte index. Locating an entry, in a buffer, the entry including the ESID of the effective address. Based on the entry including a radix page table pointer (RPTP), performing, using the RPTP to locate a translation table of a hierarchy of translation tables, using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory, and based on the obtained address, performing the requested access to the desired block of memory.

公开(公告)号：US09779028B1

公开(公告)日：2017-10-03

申请号：US15088302

申请日：2016-04-01

Applicant: Cavium, Inc.

Inventor： Shubhendu Sekhar Mukherjee ,  Mike Bertone

IPC: G06F12/06 ,  G06F12/1045 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/452 ,  G06F2212/651 ,  G06F2212/682 ,  G06F2212/683

Abstract: Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs) consisting of fewer than all VAs associated with a first set of translation context (TC) values, searching VA-indexed structure(s) to find and invalidate any entries that correspond to a VA in the subset; in response to determining that a second IM applies to all VAs associated with a second set of TC values and that no entry exists in invalidation-tracking structure(s) corresponding to the second set, bypassing searching any VA-indexed structure(s); and in response to determining that a third IM applies to all VAs associated with a third set of TC values and that at least one entry exists in the invalidation-tracking structure(s) corresponding to the third set, storing invalidation information in the invalidation-tracking structure(s) to invalidate the third set and delaying searching any VA-indexed structure(s).

公开(公告)号：US20170277639A1

公开(公告)日：2017-09-28

申请号：US15361335

申请日：2016-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amro Awad ,  Sergey Blagodurov ,  Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/65 ,  G06F2212/683

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB). During operation, the computing device updates an entry in the TLB based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. The computing device then computes, based on a lease length expression, a lease length for the entry in the TLB. Next, the computing device sets, for the entry in the TLB, a lease value to the lease length, wherein the lease value represents a time until a lease for the entry in the TLB expires, wherein the entry in the TLB is invalid when the associated lease has expired. The computing device then uses the lease value to control operations that are allowed to be performed using information from the entry in the TLB.

公开(公告)号：US09754668B1

公开(公告)日：2017-09-05

申请号：US15059733

申请日：2016-03-03

Applicant: FlashSilicon Incorporation

Inventor： Lee Wang

IPC: G11C15/04 ,  G11C7/22 ,  G11C5/06 ,  G06F12/1027 ,  G06F12/10 ,  G11C15/00 ,  G06F12/1036

CPC classification number: G11C7/22 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1036 ,  G11C11/005 ,  G11C11/54 ,  G11C13/0002 ,  G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for parallel processing digital signals directly by the processor's memory content and memory perception in one feed-forward step is disclosed. The digital perceptron device of the invention applies the configurable content and perceptive non-volatile memory arrays as the memory processor hardware. The input digital signals are then broadcasted into the non-volatile content memory array for a match to output the digital signals from the perceptive non-volatile memory array as the content-perceptive digital perceptron device.

公开(公告)号：US20170235678A1

公开(公告)日：2017-08-17

申请号：US15362820

申请日：2016-11-29

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F12/1036 ,  G06F12/0891 ,  G06F9/455 ,  G06F12/123 ,  G06F12/109 ,  G06F12/1045 ,  G06F12/0804

CPC classification number: G06F12/1036 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4843 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1063 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/30 ,  G06F2212/50 ,  G06F2212/604 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.