公开(公告)号：US5381306A

公开(公告)日：1995-01-10

申请号：US109650

申请日：1993-08-20

Applicant: Richard A. Schumacher ,  James R. Day

Inventor： Richard A. Schumacher ,  James R. Day

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H01K3/10

CPC classification number: H05K1/0265 ,  H05K1/115 ,  H05K1/116 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K3/429 ,  Y10T29/49162

Abstract: Disclosed is an apparatus and method for delivering power utilizing a multiplane power via matrix wherein the vias are each interconnected on each of the planes through which they pass such that a current flowing along any particular via, or via group, is free to either continue along its current path, or to move across any of the planes as a function of least resistance. The invention provides a system of vias for transferring power from any particular first plane to any desired second plane.

Abstract translation: 公开了一种利用多平面功率通过矩阵传递功率的装置和方法，其中通孔各自在它们通过的每个平面上互连，使得沿着任何特定通孔或通孔组流动的电流可以自由地沿着 其当前路径，或者作为最小电阻的函数移动通过任何平面。 本发明提供一种用于将功率从任何特定的第一平面传送到任何期望的第二平面的通孔系统。

公开(公告)号：US5341274A

公开(公告)日：1994-08-23

申请号：US477322

申请日：1990-02-08

Applicant: Fumio Nakatani ,  Shinichi Wakita ,  Hisatoshi Murakami ,  Tsunehiko Terada ,  Shohei Morimoto

Inventor： Fumio Nakatani ,  Shinichi Wakita ,  Hisatoshi Murakami ,  Tsunehiko Terada ,  Shohei Morimoto

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16 ,  H05K3/34 ,  H05K3/46 ,  H05K9/00

CPC classification number: H05K1/0216 ,  H05K1/0218 ,  H05K1/162 ,  H05K9/0039 ,  H05K1/095 ,  H05K1/117 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09272 ,  H05K2201/09672 ,  H05K2201/10689 ,  H05K3/3447 ,  H05K3/4644 ,  H05K3/4664 ,  Y10S428/901

Abstract: The radiation noise suppression effect is enhanced by providing an insulation layer which is formed so that the circuit pattern is covered excepting at least a part of power source pattern or ground pattern on the substrate on which circuit pattern is formed, and a conductive layer which is formed so as to be connected to the uninsulated part of the power source pattern or the ground pattern on the insulation layer, by modifying pattern shape of the conductive layer and the insulation layer or by increasing or reducing the number of these layers.

Abstract translation: 辐射噪声抑制效果通过提供形成为使得电路图案被覆盖的绝缘层，除了在其上形成电路图案的基板上的至少一部分电源图案或接地图案之外，导电层是 通过改变导电层和绝缘层的图案形状，或者通过增加或减少这些层的数量，形成为连接到电源图案的未绝缘部分或绝缘层上的接地图案。

公开(公告)号：US5172304A

公开(公告)日：1992-12-15

申请号：US795713

申请日：1991-11-21

Applicant: Jyuichiro Ozawa ,  Kikuo Wakino

Inventor： Jyuichiro Ozawa ,  Kikuo Wakino

IPC: H05K1/03 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K1/0373 ,  H05K1/167 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09672 ,  H05K3/4611

Abstract: A flat capacitor-containing wiring board, which can be arranged optionally in the interior of a multilayer substrate. This capacitor-containing wiring board has a dielectric substrate which is made of a mixture of dielectric powder and resin, and conductors which are provided on both major surfaces of the dielectric substrate. The conductors can be etched and shaped so as to form capacitors which use the interior of the wiring board as their dielectric layers. With this wiring board, it is possible to etch the conductors so that the values of the capacitors can be freely selected over a wide range, the wiring board is flexible to some extent, and no pinholes or defects are defined over a wide area. Preferably, the board has a greater relative resin content near its surfaces than in its interior, which improves the dielectric characteristics of the board. The increased resin content may be provided by resin adhesive layers on the surfaces which permeate the board to some extent.

Abstract translation: 一种扁平的含电容器的布线板，其可选地布置在多层基板的内部。 该含电容器的布线基板具有由电介质粉末和树脂的混合物构成的电介质基板和设置在电介质基板的两个主表面上的导体。 可以对导体进行蚀刻和成形，以形成使用布线板的内部作为其电介质层的电容器。 利用该布线板，可以蚀刻导体，使得可以在宽范围内自由选择电容器的值，布线板在一定程度上是柔性的，并且在广泛的区域上没有限定针孔或缺陷。 优选地，板在其表面附近具有比在其内部更大的相对树脂含量，这改善了板的介电特性。 增加的树脂含量可以通过在一定程度上渗透到板的表面上的树脂粘合剂层来提供。

公开(公告)号：US4807036A

公开(公告)日：1989-02-21

申请号：US74003

申请日：1987-07-16

Applicant: Hisashi Osada ,  Hideaki Fujioka ,  Ikuo Kato ,  Yoshinari Yamashita

Inventor： Hisashi Osada ,  Hideaki Fujioka ,  Ikuo Kato ,  Yoshinari Yamashita

IPC: H04N9/64 ,  H05K1/02 ,  H05K1/03 ,  H05K1/16 ,  H04N5/62

CPC classification number: H05K1/162 ,  H04N9/646 ,  H05K1/0233 ,  H05K1/0306 ,  H05K2201/09672 ,  H05K2201/1003 ,  H05K2201/10946

Abstract: A complex circuit component for a video signal circuit in a television receiver set has a single substrate, on which a first ceramic trap for removing speech carrier wave together with an inductor for that trap, a second trap for removing color subcarrier wave, and a delay circuit coupled with output of said second trap are mounted. The capacitors for those circuits are implemented by a pair of conductive patterns deposited on front surface and rear surface of the substrate. The capacitor for said first ceramic trap is subject to trimming so that the characteristics of the trap is adjustable.

Abstract translation: 用于电视接收机组中的视频信号电路的复杂电路部件具有单个基板，用于去除语音载波的第一陶瓷陷阱与该陷波器的电感器一起，用于去除彩色副载波的第二陷波器和延迟 与所述第二陷阱的输出耦合的电路被安装。 用于这些电路的电容器由沉积在基板的前表面和后表面上的一对导电图案来实现。 用于所述第一陶瓷捕集器的电容器进行修整，使得阱的特性是可调节的。

公开(公告)号：US4558285A

公开(公告)日：1985-12-10

申请号：US598040

申请日：1984-04-09

Applicant: Mukunda B. Shrestha ,  Geoffrey N. Mendenhall

Inventor： Mukunda B. Shrestha ,  Geoffrey N. Mendenhall

IPC: H03F1/56 ,  H03H7/38 ,  H05K1/16 ,  H03F3/60

CPC classification number: H05K1/165 ,  H03F1/56 ,  H03H7/38 ,  H05K1/162 ,  H05K2201/09672

Abstract: A broad-band impedance-matching device for an RF vacuum tube power amplifier incorporates a circuit having multiple inductors and capacitors interconnected in an impedance-matching circuit, said circuit having a low impedance input and high impedance output and made up of a plurality of series connected inductors and capacitors. Impedance transformation is performed in a number of small steps, which enables the use of a much lower cue than would be necessary if the impedance transformation were done in a single step. The arrangement produces an impedance transformation which holds over a relatively broad band width, making in unnecessary for any fine tuning of the network.

Abstract translation: 用于RF真空管功率放大器的宽带阻抗匹配装置包括具有在阻抗匹配电路中互连的多个电感器和电容器的电路，所述电路具有低阻抗输入和高阻抗输出，并由多个系列 连接电感和电容。 在许多小步骤中执行阻抗变换，如果在单个步骤中进行阻抗转换，则可以使用比所需的更低的提示。 该布置产生阻塞变换，其保持在相对宽的带宽上，使得对于网络的任何微调都是不必要的。

公开(公告)号：US4217155A

公开(公告)日：1980-08-12

申请号：US961314

申请日：1978-11-16

Applicant: William B. Fritz ,  John R. Hopkins

Inventor： William B. Fritz ,  John R. Hopkins

IPC: H01B7/08 ,  H01R12/70 ,  H05K1/02 ,  H05K1/11 ,  H05K1/16 ,  B32B31/10 ,  H01B13/06

CPC classification number: H01R23/667 ,  H01B7/08 ,  H01B7/0838 ,  H05K1/0228 ,  H05K1/118 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09709 ,  Y10T428/24132

Abstract: An improved cable having low crosstalk characteristics is comprised of a pair of multi-conductor cable members laminated together with the pairs of wires of and between the respective cable members being so spaced as to effectively form a balanced capacitive bridge configuration. The conductors of the cable members can be either round or flat in section and the cable members are preferably secured together across their entire width by means which allows the cables to be readily separated at the termination. This capability for separation of the cable members is also effective for inserting a tap means intermediate the ends of the cable.

Abstract translation: 具有低串扰特性的改进的电缆由一对多导体电缆构件组成，所述一对多导体电缆构件与各个电缆构件之间的电线对成层叠在一起，以便有效地形成平衡的电容桥结构。 电缆构件的导体可以是圆形或扁平的部分，并且电缆构件优选地通过允许电缆在终端处容易地分离的整个宽度固定在一起。 用于分离电缆构件的这种能力对于在电缆的端部之间插入抽头装置也是有效的。

公开(公告)号：US3732100A

公开(公告)日：1973-05-08

申请号：US3732100D

申请日：1971-10-18

Applicant: ITEK CORP

Inventor： GENTHE J

IPC: G03C1/705 ,  G03G17/02 ,  H01G13/00 ,  H01L49/02 ,  H05K1/00 ,  H05K1/16 ,  H05K3/18 ,  G03C5/00 ,  G03C11/00

CPC classification number: H05K3/185 ,  G03C1/705 ,  G03G17/02 ,  H01G13/00 ,  H01L49/02 ,  H05K1/0393 ,  H05K1/162 ,  H05K3/1266 ,  H05K2201/0209 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/0517

Abstract: AN ELECTRICAL COMPONENT PRODUCTION METHOD WHEREIN AN ELECTRICALLY CONDUCTIVE IMAGE ELECTRODE IS EXPOSED AND PHOTOGRAPHICALLY DEVELOPED ON THE SURFACE OF A SUBSTRATE SUPPORTED PHOTOCONDUCTIVE LAYER.

公开(公告)号：US11917758B2

公开(公告)日：2024-02-27

申请号：US17559219

申请日：2021-12-22

Applicant: PANELSEMI CORPORATION

Inventor： Ya-Che Hsueh

IPC: H05K1/11 ,  H01L25/075 ,  H05K3/40 ,  H05K3/34 ,  H05K1/18 ,  H01L33/62

CPC classification number: H05K1/116 ,  H01L25/0753 ,  H05K3/3447 ,  H05K3/4046 ,  H01L33/62 ,  H05K1/18 ,  H05K2201/09672 ,  H05K2201/10106 ,  H05K2201/10287 ,  H05K2203/0156

Abstract: A substrate structure, a manufacturing method thereof, and an electronic device. The substrate structure includes a substrate, conductive wires and conductive members. Multiple through holes penetrate through the substrate body of the substrate. Multiple first conductive pads are arranged on the first surface of the substrate body. Multiple second conductive pads are arranged on the second surface of the substrate body. The conductive wires are accommodated in the through holes and each has a first end in the first opening of corresponding through hole and a second end in the second opening of corresponding through hole. The conductive members are distributed on the first and second surfaces, and both ends thereof are connected to the corresponding first and second conductive pads through the conductive members. At least part of each conductive wire does not contact the hole wall of each through hole in a direct manner.

公开(公告)号：US11735346B2

公开(公告)日：2023-08-22

申请号：US16116963

申请日：2018-08-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shingo Ito ,  Kuniaki Yosui

IPC: H01F17/00 ,  H01L23/498 ,  H01L21/48 ,  H01F27/28 ,  H01F27/29 ,  H05K1/02 ,  H05K1/16 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01F17/0013 ,  H01F27/2804 ,  H01F27/292 ,  H01L21/4857 ,  H01L23/49822 ,  H05K1/0268 ,  H05K1/165 ,  H05K1/18 ,  H05K3/4632 ,  H01F2027/2809 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/09672

Abstract: A multilayer substrate includes at least three coil conductors respectively patterned on different surfaces of a first main surface of a laminated body, a second main surface of the laminated body, and laminated interfaces of insulating base materials and that are arranged in a lamination direction. The at least three coil conductors include first and second coil conductors, and are connected in series between first and second external electrodes. A surface at which another coil conductor is provided is not interposed between two surfaces at which the first and second coil conductors are provided, respectively. Further, the first and second coil conductors are directly connected to the first and second external electrodes, respectively, without another coil conductor interposed therebetween.

公开(公告)号：US10074938B2

公开(公告)日：2018-09-11

申请号：US15470186

申请日：2017-03-27

Applicant: CommScope Technologies LLC

Inventor： David Patrick Murray ,  Bernard Harold Hammond, Jr.

IPC: H01R13/64 ,  H01R13/6466 ,  H05K1/02 ,  H01R13/66 ,  H01R24/64

CPC classification number: H01R13/6466 ,  H01R13/6461 ,  H01R13/6464 ,  H01R13/6658 ,  H01R13/6691 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/53209

Abstract: Methods and systems for providing crosstalk compensation in a jack are disclosed. According to one method, the crosstalk compensation is adapted to compensate for undesired crosstalk generated at a capacitive coupling located at a plug inserted within the jack. The method includes positioning a first capacitive coupling a first time delay away from the capacitive coupling of the plug, the first capacitive coupling having a greater magnitude and an opposite polarity as compared to the capacitive coupling of the plug. The method also includes positioning a second capacitive coupling at a second time delay from the first capacitive coupling, the second time delay corresponding to an average time delay that optimizes near end crosstalk. The second capacitive coupling has generally the same overall magnitude but an opposite polarity as compared to the first capacitive coupling, and includes two capacitive elements spaced at different time delays from the first capacitive coupling.