公开(公告)号：US08762632B2

公开(公告)日：2014-06-24

申请号：US13336342

申请日：2011-12-23

Applicant: Sandeep Rohilla

Inventor： Sandeep Rohilla

IPC: G06F12/00

CPC classification number: G06F13/287 ,  G11C7/10 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1087

Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

Abstract translation: 在顺序写入随机读取系统中管理存储单元存储器（SCM）的输入总线流量存储器时，优先级编码器系统可用于在顺序写入步骤中找到下一个空单元。 SCM中的每个单元格都有一个位，表示单元格是满还是空。 优先编码器使用这些位和当前写指针对下一个空单元进行编码。 优先编码器还可以通过耦合到耦合到每组单元的AND运算符来找到下一组空单元。 此外，单元定位器选择器根据操作码，通过将小于等于小于SCM大小的优先编码器的单元位置输出相加0来选择各种尺寸的单元组的优先编码器中的下一个空单元位置。

公开(公告)号：US20110299346A1

公开(公告)日：2011-12-08

申请号：US12793583

申请日：2010-06-03

Applicant: Ryan Fung ,  Joshua David Fender

Inventor： Ryan Fung ,  Joshua David Fender

IPC: G11C7/00 ,  H03K19/00

CPC classification number: G11C7/222 ,  G11C7/1036 ,  G11C7/1078 ,  G11C7/1093

Abstract: An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.

Abstract translation: 一种装置包括耦合到电子装置的接口电路。 接口电路使用选通信号提供与电子设备的源同步通信。 接口电路被配置为对选通信号进行门控，以便与电子设备成功通信。

公开(公告)号：US08036059B2

公开(公告)日：2011-10-11

申请号：US11594562

申请日：2006-11-08

Applicant: Stefan Dietrich

Inventor： Stefan Dietrich

IPC: G11C7/00

CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C7/106 ,  G11C7/1066

Abstract: A circuit arrangement for reading out data time delayed from a semiconductor memory comprises a common data input at which read data, which are read out of a semiconductor memory, are present and a data buffer FIFO for buffering the read data. The buffer FIFI comprises a plurality of FIFO modules each comprising a plurality of individual FIFO cells. Each FIFO module can be addressed via respective allocated first input and output pointers and each FIFO cell can be addressed via respective allocated second input and output pointers. The circuit arrangement further comprises a controllable read latency generator generating the first and second output pointers for driving the FIFO modules and FIFO cells with a read latency predetermined with reference to the first and second input pointers, respectively, and a common data output at which the read data are present time-delayed in dependence on the predetermined read latency.

Abstract translation: 用于读出从半导体存储器延迟的数据的电路装置包括：公共数据输入端，存储从半导体存储器读出的读取数据，以及用于缓冲读取数据的数据缓冲器FIFO。 缓冲器FIFI包括多个FIFO模块，每个FIFO模块包括多个单独的FIFO单元。 可以通过相应分配的第一输入和输出指针来寻址每个FIFO模块，并且可以通过相应分配的第二输入和输出指针来寻址每个FIFO单元。 该电路装置还包括一个可控读延迟发生器，分别产生用于驱动FIFO模块和FIFO单元的第一和第二输出指针，其具有参考第一和第二输入指针预定的读等待时间，以及公共数据输出， 读取数据根据预定的读取等待时间延迟。

公开(公告)号：US07974124B2

公开(公告)日：2011-07-05

申请号：US12490655

申请日：2009-06-24

Applicant: Hardwell Chibvongodze ,  Manabu Sakai ,  Teruhiko Kamei

Inventor： Hardwell Chibvongodze ,  Manabu Sakai ,  Teruhiko Kamei

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C11/5642 ,  G11C7/103 ,  G11C7/1036 ,  G11C19/00

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. To control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.

Abstract translation: 选择存储器单元阵列的电路用于保持存储单元的读取数据或写入数据。 在第一组实施例中，具有阵列列的移位寄存器链具有以循环布置的列。 例如，当指针沿着阵列的第一方向移动时，可以评估每隔一列或列组，随着指针在另一个方向上向后移动，另外一半的列被访问。 另一组实施例将列分成两组，并且使用一对交错指针，每半组一列，以半速计时。 为了控制两个组的访问，每个集合都连接到相应的中间数据总线。 然后将中间数据总线连接到以全速计时的组合数据总线。

公开(公告)号：US20100329007A1

公开(公告)日：2010-12-30

申请号：US12490655

申请日：2009-06-24

Applicant: Hardwell Chibvongodze ,  Manabu Sakai ,  Teruhiko Kamei

Inventor： Hardwell Chibvongodze ,  Manabu Sakai ,  Teruhiko Kamei

IPC: G11C16/04 ,  G11C7/10 ,  G11C8/18 ,  G11C7/00

CPC classification number: G11C11/5642 ,  G11C7/103 ,  G11C7/1036 ,  G11C19/00

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. to control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.

Abstract translation: 选择存储器单元阵列的电路用于保持存储单元的读取数据或写入数据。 在第一组实施例中，具有阵列列的移位寄存器链具有以循环布置的列。 例如，当指针沿着阵列的第一方向移动时，可以评估每隔一列或列组，随着指针在另一个方向上向后移动，另外一半的列被访问。 另一组实施例将列分成两组，并且使用一对交错指针，每半组一列，以半速计时。 以控制两组的访问，每一组连接到相应的中间数据总线。 然后将中间数据总线连接到以全速计时的组合数据总线。

公开(公告)号：US07747914B2

公开(公告)日：2010-06-29

申请号：US11980442

申请日：2007-10-31

Applicant: Yong-woon Han ,  Ki-am Lee

Inventor： Yong-woon Han ,  Ki-am Lee

IPC: G11C29/00

CPC classification number: G11C29/44 ,  G11C7/1036 ,  G11C11/41 ,  G11C2029/2602

Abstract: According to an example embodiment, a memory diagnosis test circuit may include a memory core block, a word line selector, a bit line selector, and/or an analog mode control unit. The memory core block may include a plurality of memory cells. The word line selector may be configured to select one of a plurality of word lines of the memory core block using a first shift register. The bit line selector may be configured to select one of a plurality of bit line pairs of the memory core block using a second shift register. The analog mode control unit may be configured to monitor data corresponding to the selected word line and bit line pair.

Abstract translation: 根据示例实施例，存储器诊断测试电路可以包括存储器核心块，字线选择器，位线选择器和/或模拟模式控制单元。 存储器核心块可以包括多个存储器单元。 字线选择器可以被配置为使用第一移位寄存器来选择存储器核心块的多个字线中的一个。 位线选择器可以被配置为使用第二移位寄存器来选择存储器核心块的多个位线对之一。 模拟模式控制单元可以被配置为监视与所选字线和位线对相对应的数据。

公开(公告)号：US07684225B2

公开(公告)日：2010-03-23

申请号：US11549178

申请日：2006-10-13

Applicant: Ward Parkinson

Inventor： Ward Parkinson

IPC: G11C17/00

CPC classification number: G11C16/26 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/1075 ,  G11C11/4096 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0076

Abstract: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh. In some embodiments, the circuitry may further include shift registers and one or more arithmetic logic units to provide a video memory.

Abstract translation: 布置在逻辑列和逻辑行中的非易失性存储器单元的阵列，以及相关联的电路，以使得能够并行地读取或写入行上的一个或多个存储器单元。 在一些实施例中，存储器单元阵列可以包括相变材料。 在一些实施例中，电路可以包括写入驱动器，读取驱动器，读出放大器以及通过扩展刷新来将存储器单元与读出放大器隔离的电路。 在一些实施例中，电路还可以包括移位寄存器和一个或多个算术逻辑单元以提供视频存储器。

公开(公告)号：US07586793B2

公开(公告)日：2009-09-08

申请号：US11241000

申请日：2005-09-29

Applicant: Raul-Adrian Cernea

Inventor： Raul-Adrian Cernea

IPC: G11C7/00

CPC classification number: G11C16/06 ,  G11C7/1036 ,  G11C7/1051 ,  G11C19/00 ,  G11C19/28

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit. And while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell.

Abstract translation: 选择存储器单元阵列的电路用于保持存储单元的读取数据或写入数据。 存储单元可以是多状态存储器单元。 有一个移位寄存器链，具有数组列的阶段。 选通脉冲通过该移位寄存器移位。 每个时钟的选通点依次处于并使能不同的选择电路。 那个已经被选通使能的特定选择电路然后将执行一定的功能。 在读取模式下，所选择的选择电路将存储的信息发送到输出缓冲器，以从集成电路输出。 而在编程模式下，所选择的选择电路将从输入缓冲器接收数据。 该数据将被写入存储单元。

公开(公告)号：US07565588B2

公开(公告)日：2009-07-21

申请号：US11607029

申请日：2006-12-01

Applicant: Katsuya Nakashima ,  Kazuhiro Suzuki ,  Satoshi Yamakawa ,  Toshiyuki Nishihara ,  Yukihisa Tsuneda

Inventor： Katsuya Nakashima ,  Kazuhiro Suzuki ,  Satoshi Yamakawa ,  Toshiyuki Nishihara ,  Yukihisa Tsuneda

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C7/1036 ,  G11C7/1039 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/846 ,  G11C2216/14

Abstract: A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer configured to latch read data of the cell array in units of pages; an output circuit configured to output read data; and a data transfer circuit configured to sequentially transfer read data in units of pages latched in the buffer to the output circuit, wherein the data transfer circuit includes: at least one layer of a scan register train including a plurality of serially connected scan registers having a register and a multiplexer connected to each other to operate for each of clocks, wherein an output of the multiplexer is connected to an input of a register, and an input of a multiplexer is connected to an output of a register in a next previous stage.

Abstract translation: 提供半导体器件和数据存储装置。 半导体器件包括：单元阵列，配置成具有排列成阵列的数据存储单元; 至少一个缓冲器被配置为以页为单位来锁存所述单元阵列的读取数据; 输出电路，被配置为输出读取数据; 以及数据传送电路，被配置为将读取的数据以缓存器中的锁存的页面顺序地传送到输出电路，其中数据传送电路包括：至少一层扫描寄存器串，其包括多个串行连接的扫描寄存器， 寄存器和多路复用器相互连接以对每个时钟进行操作，其中多路复用器的输出连接到寄存器的输入，并且多路复用器的输入连接到下一个前一级的寄存器的输出。

公开(公告)号：US07420855B2

公开(公告)日：2008-09-02

申请号：US11724210

申请日：2007-03-15

Applicant: Munenori Nakamura

Inventor： Munenori Nakamura

IPC: G11C7/10

CPC classification number: G11C7/1036 ,  G11C7/1051 ,  G11C7/106 ,  G11C2207/107

Abstract: Reducing power consumption of a semiconductor memory device having a serial interface is disclosed. After parallel read-out data from a memory-cell matrix 14 are held in a data latch 17, the parallel read-out data are selected sequentially by a serial output selector 18 according to timing signals SL0-SL15 from a controller 20 and are outputted serially from an output buffer 19 as an output data DO. In an activating control unit 23, outputting an operation control signal AC to a gate-voltage generating unit 21, a drain-voltage generating unit 22, and a sense amplifier 16 is being halted during from when a timing signal SL0 is finished to when a timing SL10 is finished. Consequently, during the above mentioned period, the unnecessary operations of the gate-voltage generating unit 21, the drain-voltage generating unit 22, and the sense amplifier 16 are being halted and then the power consumption thereof can be reduced.

Abstract translation: 公开了具有串行接口的半导体存储器件的功耗的降低。 在来自存储单元矩阵14的并行读出数据被保存在数据锁存器17中之后，串行输出选择器18根据来自控制器20的定时信号SL 0 -SL 15依次选择并行读出数据，以及 作为输出数据DO从输出缓冲器19串行地输出。 在激活控制单元23中，在定时信号SL 0完成到当时，从门电压产生单元21输出操作控制信号AC，漏极电压产生单元22和读出放大器16正在停止 时序SL10完成。 因此，在上述期间，栅极电压产生部21，漏极电压产生部22以及读出放大器16的不必要的动作停止，能够降低功耗。