公开(公告)号：US20080062789A1

公开(公告)日：2008-03-13

申请号：US11980442

申请日：2007-10-31

Applicant: Yong-woon Han ,  Ki-am Lee

Inventor： Yong-woon Han ,  Ki-am Lee

IPC: G11C11/00 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C29/44 ,  G11C7/1036 ,  G11C11/41 ,  G11C2029/2602

Abstract: According to an example embodiment, a memory diagnosis test circuit may include a memory core block, a word line selector, a bit line selector, and/or an analog mode control unit. The memory core block may include a plurality of memory cells. The word line selector may be configured to select one of a plurality of word lines of the memory core block using a first shift register. The bit line selector may be configured to select one of a plurality of bit line pairs of the memory core block using a second shift register. The analog mode control unit may be configured to monitor data corresponding to the selected word line and bit line pair.

Abstract translation: 根据示例实施例，存储器诊断测试电路可以包括存储器核心块，字线选择器，位线选择器和/或模拟模式控制单元。 存储器核心块可以包括多个存储器单元。 字线选择器可以被配置为使用第一移位寄存器来选择存储器核心块的多个字线中的一个。 位线选择器可以被配置为使用第二移位寄存器来选择存储器核心块的多个位线对之一。 模拟模式控制单元可以被配置为监视与所选字线和位线对相对应的数据。

公开(公告)号：US07313035B2

公开(公告)日：2007-12-25

申请号：US11030881

申请日：2005-01-10

Applicant: William Thomas Lynch ,  David James Herbison

Inventor： William Thomas Lynch ,  David James Herbison

IPC: G11C7/00

CPC classification number: G11C29/32 ,  G06F13/1673 ,  G11C7/1036 ,  G11C29/12 ,  G11C29/1201 ,  G11C2029/3202

Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

公开(公告)号：US20070130488A1

公开(公告)日：2007-06-07

申请号：US11607029

申请日：2006-12-01

Applicant: Katsuya Nakashima ,  Kazuhiro Suzuki ,  Satoshi Yamakawa ,  Toshiyuki Nishihara ,  Yukihisa Tsuneda

Inventor： Katsuya Nakashima ,  Kazuhiro Suzuki ,  Satoshi Yamakawa ,  Toshiyuki Nishihara ,  Yukihisa Tsuneda

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C7/1036 ,  G11C7/1039 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/846 ,  G11C2216/14

Abstract: A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer configured to latch read data of the cell array in units of pages; an output circuit configured to output read data; and a data transfer circuit configured to sequentially transfer read data in units of pages latched in the buffer to the output circuit, wherein the data transfer circuit includes: at least one layer of a scan register train including a plurality of serially connected scan registers having a register and a multiplexer connected to each other to operate for each of clocks, wherein an output of the multiplexer is connected to an input of a register, and an input of a multiplexer is connected to an output of a register in a next previous stage.

Abstract translation: 提供半导体器件和数据存储装置。 半导体器件包括：单元阵列，配置成具有排列成阵列的数据存储单元; 至少一个缓冲器被配置为以页为单位来锁存所述单元阵列的读取数据; 输出电路，被配置为输出读取数据; 以及数据传送电路，被配置为将读取的数据以缓存器中的锁存的页面顺序地传送到输出电路，其中数据传送电路包括：至少一层扫描寄存器串，其包括多个串行连接的扫描寄存器， 寄存器和多路复用器相互连接以对每个时钟进行操作，其中多路复用器的输出连接到寄存器的输入，并且多路复用器的输入连接到下一个前一级的寄存器的输出。

公开(公告)号：US20070121393A1

公开(公告)日：2007-05-31

申请号：US11594562

申请日：2006-11-08

Applicant: Stefan Dietrich

Inventor： Stefan Dietrich

IPC: G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C7/106 ,  G11C7/1066

Abstract: A circuit arrangement for reading out data time delayed from a semiconductor memory comprises a common data input at which read data, which are read out of a semiconductor memory, are present and a data buffer FIFO for buffering the read data. The buffer FIFI comprises a plurality of FIFO modules each comprising a plurality of individual FIFO cells. Each FIFO module can be addressed via respective allocated first input and output pointers and each FIFO cell can be addressed via respective allocated second input and output pointers. The circuit arrangement further comprises a controllable read latency generator generating the first and second output pointers for driving the FIFO modules and FIFO cells with a read latency predetermined with reference to the first and second input pointers, respectively, and a common data output at which the read data are present time-delayed in dependence on the predetermined read latency.

Abstract translation: 用于读出从半导体存储器延迟的数据的电路装置包括：公共数据输入端，存储从半导体存储器读出的读取数据，以及用于缓冲读取数据的数据缓冲器FIFO。 缓冲器FIFI包括多个FIFO模块，每个FIFO模块包括多个单独的FIFO单元。 可以通过相应分配的第一输入和输出指针来寻址每个FIFO模块，并且可以通过相应分配的第二输入和输出指针来寻址每个FIFO单元。 该电路装置还包括一个可控读延迟发生器，分别产生用于驱动FIFO模块和FIFO单元的第一和第二输出指针，其具有参考第一和第二输入指针预定的读等待时间，以及公共数据输出， 读取数据根据预定的读取等待时间延迟。

公开(公告)号：US07170802B2

公开(公告)日：2007-01-30

申请号：US10751097

申请日：2003-12-31

Applicant: Raul-Adrian Cernea ,  Yan Li

Inventor： Raul-Adrian Cernea ,  Yan Li

IPC: G11C29/00

CPC classification number: G11C7/1036 ,  G11C29/848

Abstract: A non-volatile memory wherein bad columns in the array of memory cells can be removed. Substitute redundant columns can replace the removed columns. Both of these processes are performed on the memory in a manner that is externally transparent and, consequently, need not be managed externally by the host or controller to which the memory is attached. The bad column can be maintained on the memory. At power up, the list of bad columns is used to fuse out the bad columns. The memory may also contain a number of redundant columns that can be used to replace the bad columns.

Abstract translation: 可以去除存储器单元阵列中的不良列的非易失性存储器。 替换冗余列可以替换已删除的列。 这些处理都以外部透明的方式在存储器上执行，因此不需要由附加存储器的主机或控制器在外部进行管理。 内存中可以维护坏列。 上电时，不良列的列表用于对不良列进行融合。 内存还可能包含一些可用于替换不良列的冗余列。

公开(公告)号：US20060152979A1

公开(公告)日：2006-07-13

申请号：US11299758

申请日：2005-12-13

Applicant: Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

Inventor： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC: G11C7/00

CPC classification number: G11C7/1036 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

Abstract: A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is configured to receive a clock signal and a first control signal, and output a plurality of data in response to the clock signal after the first control signal is asserted. After the first control signal is asserted, an internal signal which responds to the clock signal transits N times (N is a positive integer and greater than or equal to 2), then output of the data is started. At least one of the data is output at the transition after the output begins.

公开(公告)号：US07061827B2

公开(公告)日：2006-06-13

申请号：US10688881

申请日：2003-10-21

Applicant: Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

Inventor： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC: G11C11/00

CPC classification number: G11C7/1036 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

Abstract: A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is configured to receive a clock signal and a first control signal, and output a plurality of data in response to the clock signal after the first control signal is asserted. After the first control signal is asserted, an internal signal which responds to the clock signal transits N times (N is a positive integer and greater than or equal to 2), then output of the data is started. At least one of the data is output at the transition after the output begins.

Abstract translation: 半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列具有以行和列排列的多个存储单元。 存储单元存储数据，并根据地址信号进行选择。 控制电路被配置为接收时钟信号和第一控制信号，并且在第一控制信号被断言之后响应于时钟信号输出多个数据。 在第一控制信号置位之后，响应时钟信号的内部信号转换N次（N为正整数，大于或等于2），则数据的输出开始。 在输出开始后的转换中输出至少一个数据。

公开(公告)号：US06985388B2

公开(公告)日：2006-01-10

申请号：US10818887

申请日：2004-04-05

Applicant: Raul-Adrian Cernea

Inventor： Raul-Adrian Cernea

IPC: G11C11/34

CPC classification number: G11C16/06 ,  G11C7/1036 ,  G11C7/1051 ,  G11C19/00 ,  G11C19/28

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit. And while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell.

公开(公告)号：US20050182914A1

公开(公告)日：2005-08-18

申请号：US11103698

申请日：2005-04-11

Applicant: Masashi Hashimoto ,  Gene Frantz ,  John Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene Frantz ,  John Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G06F12/06

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US06879526B2

公开(公告)日：2005-04-12

申请号：US10284198

申请日：2002-10-31

Applicant: William Thomas Lynch ,  David James Herbison

Inventor： William Thomas Lynch ,  David James Herbison

IPC: G06F13/16 ,  G11C7/10 ,  G11C29/12 ,  G11C7/00

CPC classification number: G11C29/32 ,  G06F13/1673 ,  G11C7/1036 ,  G11C29/12 ,  G11C29/1201 ,  G11C2029/3202

Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.