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    Resonant power converter
    12.
    发明授权
    Resonant power converter 有权

    公开(公告)号：US11594972B2

    公开(公告)日：2023-02-28

    申请号：US17342487

    申请日：2021-06-08

    Applicant: 3D PLUS

    Inventor： Cédric Colonna

    IPC: H02M3/335 ,  H02M1/00 ,  H02M3/337

    Abstract: A power converter having a parallel resonant circuit, includes an inverter, a resonant circuit, a transformer comprising a primary circuit and a secondary circuit, control means for the inverter, the inverter being connected to the resonant circuit, which is intended to be connected to an output load via the transformer, the power converter wherein the inverter comprises a first half-bridge and a second half-bridge in parallel with the first half-bridge, a first inductor between the first half-bridge and the resonant circuit, a second inductor between the second half-bridge and the resonant circuit, and in that the first and second inductors have the same inductance and are coupled in the opposite direction to one another.

    Process for manufacturing a 3D electronic module comprising external interconnection leads
    13.
    发明授权
    Process for manufacturing a 3D electronic module comprising external interconnection leads 有权

    公开(公告)号：US09659846B2

    公开(公告)日：2017-05-23

    申请号：US15046277

    申请日：2016-02-17

    Applicant: 3D PLUS

    Inventor： Alexandre Val ,  Fabrice Soufflet

    IPC: H01L23/495 ,  H01L21/48 ,  H01L25/10 ,  H01L21/56 ,  H01L23/31

    CPC classification number: H01L23/49575 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49551 ,  H01L23/49555 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1064

    Abstract: A process for manufacturing at least one 3D electronic module each comprises a stack of electronic packages and/or printed wiring boards, wherein a stack is placed on an electrically interconnecting system comprising metal leads each having two ends. The process comprises the following steps: starting with a lead frame that comprises metal leads, folding by about 180° the leads in order to obtain what is referred to as an internal frame portion including the folded ends, which are intended to be molded, the other portion, which is what is referred to as an external portion, including the unfolded exterior ends, the two ends of each lead being intended to emerge from the 3D module on a given face cut along Z; depositing on the leads a metal coating; placing the external portion of the frame between two, an upper and lower, protective elements while leaving the internal portion free, and placing the frame and the protective elements on a carrier; placing each stack equipped each with exterior interconnection tabs so as to superpose the exterior tabs on the internal portion; molding, in a resin, the stack, the exterior tabs and the internal portion and thereby partially covering the upper protective element; cutting the resin and thereby leaving flush conductive sections of the exterior tabs and of the ends of the leads and removing the resin from the upper protective element; metallizing the cut faces; removing the carrier; and removing the protective elements in order to expose the leads of the external portion.

    Method for positioning chips during the production of a reconstituted wafer
    14.
    发明授权
    Method for positioning chips during the production of a reconstituted wafer 有权
    在重新制造的晶片生产期间定位芯片的方法

    公开(公告)号：US08735220B2

    公开(公告)日：2014-05-27

    申请号：US13377109

    申请日：2010-06-14

    Applicant: Christian Val

    Inventor： Christian Val

    IPC: H01L21/00

    CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00

    Abstract: A method for fabricating a re-built wafer which comprises chips having connection pads, comprising: fabricating a first wafer of chips, production on this wafer of a stack of at least one layer of redistribution of the pads of the chips on conductive tracks designed for the interconnection of the chips, this stack being designated the main RDL layer, cutting this wafer in order to obtain individual chips each furnished with their RDL layer, transferring the individual chips with their RDL layer to a sufficiently rigid support to remain flat during the following steps, which support is furnished with an adhesive layer, with the RDL layer on the adhesive layer, depositing a resin in order to encapsulate the chips, polymerizing the resin, removing the rigid support, depositing a single redistribution layer called a mini RDL in order to connect the conductive tracks of the main RDL layer up to interconnection contacts, through apertures made in the adhesive layer, the wafer comprising the polymerized resin, the chips with their RDL layer and the mini RDL being the re-built wafer.

    Abstract translation: 一种用于制造重构晶片的方法，其包括具有连接焊盘的芯片，包括：制造芯片的第一晶片，在所述晶片上制造堆叠的至少一层芯片焊盘重新分布的导电轨道 芯片的互连，该堆叠被指定为主RDL层，切割该晶片以获得各自配备有RDL层的各个芯片，将具有RDL层的各个芯片传递到足够刚性的支撑件，以在下列过程中保持平坦 步骤，该支撑件配备有粘合剂层，RDL层在粘合剂层上，沉积树脂以封装芯片，聚合树脂，去除刚性载体，按顺序沉积单个再分布层，称为小型RDL 将主RDL层的导电轨道连接到互连触点，通过在粘合剂层中制成的孔，晶片包括 聚合树脂，具有RDL层的芯片和小型RDL是重新构建的晶片。

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