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公开(公告)号：US12236529B2
公开(公告)日：2025-02-25
申请号：US17562653
申请日：2021-12-27
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Christopher J. Brennan , Randy Wayne Ramsey , Nishank Pathak , Ricky Wai Yeung Iu , Jimshed Mirza , Anthony Chan
Abstract: Systems, apparatuses, and methods for implementing a discard engine in a graphics pipeline are disclosed. A system includes a graphics pipeline with a geometry engine launching shaders that generate attribute data for vertices of each primitive of a set of primitives. The attribute data is consumed by pixel shaders, with each pixel shader generating a deallocation message when the pixel shader no longer needs the attribute data. A discard engine gathers deallocations from multiple pixel shaders and determines when the attribute data is no longer needed. Once a block of attributes has been consumed by all potential pixel shader consumers, the discard engine deallocates the given block of attributes. The discard engine sends a discard command to the caches so that the attribute data can be invalidated and not written back to memory.
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公开(公告)号：US12235964B2
公开(公告)日：2025-02-25
申请号：US17098234
申请日：2020-11-13
Applicant: ATI Technologies ULC
Inventor： Srinidhi Katte Vijayendra
Abstract: A secure data recorder provides targeted collection and storage of working data from any subsystem of a computing device. The data recorder gathers and stores device working data based on stored configuration data. The configuration data indicates memory and storage locations on the device from which to gather working data and storage locations at which the data recorder stores the gathered working data. The data recorder operates in a secure execution environment during all of the pre-boot stage of the computing device. The data recorder further allows a user to update the Basic Input/Output System (BIOS) of the computing device based on a firmware image that may be received via the network. The data recorder also facilitates gathering of working data, over time, that may reveal a malfunction of particular hardware configurations and particular software configurations.
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公开(公告)号：US12216590B2
公开(公告)日：2025-02-04
申请号：US18208059
申请日：2023-06-09
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Saurabh Sharma , Hashem Hashemi , Guennadi Riguer
IPC: G06F12/08 , G06F12/0811 , G06F12/126
Abstract: A cache controller of a processing system implementing a non-uniform memory architecture (NUMA) adjusts a cache replacement priority of local and non-local data stored at a cache based on a cache replacement policy. Local data is data that is accessed by the cache via a local memory channel and non-local data is data that is accessed by the cache via a non-local memory channel. The cache controller assigns priorities to local and non-local data stored at the cache based on a cache replacement policy and selects data for replacement at the cache based, at least in part, on the assigned priorities.
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公开(公告)号：US12210891B2
公开(公告)日：2025-01-28
申请号：US17126315
申请日：2020-12-18
Inventor： Yinan Jiang , ZhenYu Min , WenWen Tang
Abstract: A processing system includes physical function circuitry to execute virtual functions and a processing unit configured to operate in a first mode that allows more than one virtual function to execute on the physical function circuitry and a second mode that constrains the physical function circuitry to executing a single virtual function. A first virtual function modifies a state of the processing unit in response to the processing unit being in the second mode. A host driver executing on the processing unit modifies an operating mode indicator to indicate that the processing unit is operating in the first mode or to indicate that the processing unit is operating in the second mode. Microcode executing on the processing unit accesses the operating mode indicator to determine whether the processing unit is operating in the first mode or the second mode.
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公开(公告)号：US20250005838A1
公开(公告)日：2025-01-02
申请号：US18345406
申请日：2023-06-30
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Michal Adam Wozniak , Guennadi Riguer
Abstract: A technique for rendering is provided. The technique includes generating a first gradient for a shade space texture tile, wherein the first gradient reflects a relationship between shade space texel spacing and screen space pixel spacing; generating a second gradient for a shade space texel of the shade space texture tile, wherein the second gradient reflects a relationship between material texel spacing and shade space texel spacing; combining the first gradient and the second gradient to obtain a third gradient; and performing anisotropic filtering on the material texture using the third gradient to obtain a value for the shade space texel.
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Patent Agency Ranking
公开(公告)号：US20250004949A1
公开(公告)日：2025-01-02
申请号：US18217291
申请日：2023-06-30
Applicant: Advanced Micro Devices, Inc , ATI Technologies ULC
Inventor： Paul Blinzer , Anthony Asaro , Nippon HarshadKumar Raval , Anthony Thomas Gutierrez , Leopold Grinberg , Millind Mittal , Samuel Richard Bayliss
IPC: G06F12/1009 , G06F12/14
Abstract: In accordance with the described techniques for extended attributes for shared page tables, a device includes an accelerator device and a memory management unit that maintains a first set of page tables and a second set of page tables. The second set of page tables includes extended attributes for accessing data that the accelerator device operates on. The memory management unit is configured to receive a virtual memory address, and translate the virtual memory address to a physical memory address using the first set of page tables. In addition, the memory management unit retrieves the extended attributes from the second set of page tables. In this way, data is accessed from the physical memory address based on the extended attributes.
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公开(公告)号：US20250004662A1
公开(公告)日：2025-01-02
申请号：US18342186
申请日：2023-06-27
Applicant: Advanced Micro Devices, Inc , ATI Technologies ULC
Inventor： David Da Wei Lin , Ronald Lee Pettyjohn , Pouya Najafi Ashtiani , Gershom Birk , Anwar Parvez Kashem
IPC: G06F3/06
Abstract: In accordance with described techniques for read gate training and tracking, a computing device includes a memory system (e.g., dynamic random access memory (DRAM)) that receives a memory read operation which includes a memory clock that correlates to a physical layer (PHY) clock. The computing device includes a PHY that receives a return data signal from the memory system, where the return data signal includes a returned data strobe that is out-of-phase with respect to the PHY clock. The computing device includes training logic that utilizes edge detection to determine an unknown clocking phase of the returned data strobe with respect to the PHY clock. The computing device also includes tracking logic that utilizes the edge detection to detect a signal drift of the delay signal with respect to the returned data strobe and compensate for the drift.
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公开(公告)号：US12184871B2
公开(公告)日：2024-12-31
申请号：US18079624
申请日：2022-12-12
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Ying Luo , Alvin Duong , Edward Harold , Wei Gao , Shu-Hsien Samuel Wu , Haibo Liu , Ehsan Mirhadi
IPC: H04N19/186 , H04N19/124 , H04N19/176 , H04N19/184 , H04N19/65
Abstract: An encoder implements a residual-free palette encoding mode in which a block of pixels is used to derive a palette table having a number of palette colors less than a number of pixel colors in the block of pixels, and to derive a color map representing each pixel of the block with a corresponding index number associated with a palette color that most closely matches the pixel's color. The calculations of residuals representing errors between the predicted palette colors and the actual pixel colors are omitted during the encoding process, thereby facilitating implementation of less complex palette mode encoder hardware at the expense of slight loss of color accuracy. Moreover, when multiple encoding modes are available, the encoder can employ the residual-free palette encoding mode when the rate-distortion cost or other cost of using this mode is determined to be the lowest cost of the plurality of encoding modes.
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公开(公告)号：US12182396B2
公开(公告)日：2024-12-31
申请号：US18192694
申请日：2023-03-30
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Christopher J. Brennan , Akshay Lahiry , Guennadi Riguer
IPC: G06F3/06
Abstract: Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range.
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公开(公告)号：US12174775B1
公开(公告)日：2024-12-24
申请号：US18083738
申请日：2022-12-19
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Padmini Nujetti , Chao Yu , Michael Tresidder , Daniel McLean
IPC: G06F13/42
Abstract: The disclosed computer-implemented method for multi-lane data bus inversion can include receiving data for transmission via a plurality of data lanes, each data lane corresponding to one of a plurality of inversion bits, and, for each data lane within the plurality of data lanes, applying the corresponding inversion bit to each bit within the data lane. Various other methods, apparatuses, and systems are also disclosed.
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