公开(公告)号：US07457241B2

公开(公告)日：2008-11-25

申请号：US10772737

申请日：2004-02-05

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

IPC: H04J1/16

CPC classification number: H04L47/60 ,  H04L47/15 ,  H04L47/50 ,  H04L47/52 ,  H04L49/90

Abstract: A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.

Abstract translation: 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

公开(公告)号：US07406080B2

公开(公告)日：2008-07-29

申请号：US10868725

申请日：2004-06-15

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

IPC: H04L12/56

CPC classification number: H04L49/90 ,  H04L49/9042 ,  H04L49/9073 ,  H04L69/22

Abstract: A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.

Abstract translation: 提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。 网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。 芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。 该方法包括利用报头信息来识别分组的其余部分的位置和范围。 当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时 有空间。

公开(公告)号：US07376809B2

公开(公告)日：2008-05-20

申请号：US11076218

申请日：2005-03-09

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

IPC: G06F12/02

CPC classification number: H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

Abstract: Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

Abstract translation: 公开了一种用于在网络处理器中实现多帧控制块的系统和方法。 实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。 随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。 帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。 网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。 每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。 由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

公开(公告)号：US20070011223A1

公开(公告)日：2007-01-11

申请号：US11133477

申请日：2005-05-18

Applicant: Jean Calvignac ,  Chih-jen Chang ,  Joseph Logan ,  Fabrice Verplanken ,  Daniel Wind

Inventor： Jean Calvignac ,  Chih-jen Chang ,  Joseph Logan ,  Fabrice Verplanken ,  Daniel Wind

IPC: G06F15/16

CPC classification number: H04L47/527 ,  H04L47/50 ,  H04L47/522 ,  H04L47/568 ,  H04L47/58

Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

Abstract translation: 提供了一种用于灵活数据流的网络处理器数据流芯片和方法。 数据流芯片包括多个片上数据传输和调度电路结构。 响应于指标选择数据传输和调度电路结构。 数据传输电路结构可以包括可选择的帧处理和数据传输功能。 可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。 调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。 在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

公开(公告)号：US20060221989A1

公开(公告)日：2006-10-05

申请号：US11096363

申请日：2005-04-01

Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin Verrilli

Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin Verrilli

IPC: G08C15/00 ,  H04L12/28 ,  H04L12/56 ,  G01R31/08 ,  H04L12/26 ,  G06F11/00 ,  H04J3/14 ,  H04J1/16 ,  H04L1/00

CPC classification number: H04L49/901 ,  H04J3/0632 ,  H04L47/50 ,  H04L49/90 ,  H04L49/9031

Abstract: A method and system for receiving packets in a computer network are disclosed. The method and system include providing at least one receive port, a buffer, a scheduler, and a wrap port. The buffer has an input coupled with the at least one receive port and an output. The scheduler has a first input coupled to the output of the buffer, a second input coupled to the wrap port, and an output.

Abstract translation: 公开了一种在计算机网络中接收分组的方法和系统。 该方法和系统包括提供至少一个接收端口，缓冲器，调度器和包装端口。 缓冲器具有与至少一个接收端口和输出端耦合的输入。 调度器具有耦合到缓冲器的输出的第一输入，耦合到包装端口的第二输入和输出。

公开(公告)号：US20060212563A1

公开(公告)日：2006-09-21

申请号：US11418606

申请日：2006-05-05

Applicant: William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

Inventor： William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

IPC: G06F15/173

CPC classification number: H04L47/10 ,  H04L47/193 ,  H04L69/12 ,  H04L69/16 ,  H04L69/161 ,  H04L69/162

Abstract: A mechanism for offloading the management of send queues in a split socket stack environment, including efficient split socket queue flow control and TCP/IP retransmission support. As consumers initiate send operations, send work queue entries (SWQEs) are created by an Upper Layer Protocol (ULP) and written to the send work queue (SWQ). The Internet Protocol Suite Offload Engine (IPSOE) is notified of a new entry to the SWQ and it subsequently reads this entry that contains pointers to the data that is to be transmitted. After the data is transmitted and acknowledgments are received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). After the CQE is written, the ULP subsequently processes the entry and removes it from the CQE, freeing up a space in both the SWQ and CQ. The number of entries available in the SWQ are monitored by the ULP so that it does not overwrite any valid entries. Likewise, the IPSOE monitors the number of entries available in the CQ, so as not overwrite the CQ. The flow control between the ULP and the IPSOE is credit based. The passing of CQ credits is the only explicit mechanism required to manage flow control of both the SWQ and the CQ between the ULP and the IPSOE.

公开(公告)号：US20060168583A1

公开(公告)日：2006-07-27

申请号：US11042692

申请日：2005-01-25

Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Harm Hofstee ,  Fabrice Verplanken ,  Colin Verrilli

Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Harm Hofstee ,  Fabrice Verplanken ,  Colin Verrilli

IPC: G06F9/46

CPC classification number: G06F9/3851 ,  G06F9/3802 ,  G06F9/4843

Abstract: Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.

Abstract translation: 公开了用于在多线程数字处理器的流水线中分发线程指令的系统和方法。 更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。 如果要选择的线程无法执行，则选择补充线程执行。

公开(公告)号：US20060146881A1

公开(公告)日：2006-07-06

申请号：US11030344

申请日：2005-01-06

Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

IPC: H04J3/00

CPC classification number: H04L49/901 ,  H04L49/90 ,  H04L49/9021

Abstract: Apparatus and method for storing network frame data which is to be modified. A plurality of buffers stores the network data which is arranged in a data structure identified by a frame control block and buffer control block. A plurality of buffer control blocks associated with each buffer storing the frame data establishes a sequence of the buffers. Each buffer control block has data for identifying a subsequent buffer within the sequence. The first buffer is identified by a field of a frame control block as well as the beginning and ending address of the frame data. The frame data can be modified without rewriting the data to memory by altering the buffer control block and/or frame control block contents without having to copy or rewrite the data in order to modify it.

公开(公告)号：US20060026342A1

公开(公告)日：2006-02-02

申请号：US10899937

申请日：2004-07-27

Applicant: Jean Calvignac ,  Chih-Jen Chang ,  Gordon Davis ,  Fabrice Verplanken

Inventor： Jean Calvignac ,  Chih-Jen Chang ,  Gordon Davis ,  Fabrice Verplanken

IPC: G06F12/00

CPC classification number: G06F13/1642

Abstract: Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.

Abstract translation: 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。

公开(公告)号：US06198535B1

公开(公告)日：2001-03-06

申请号：US09191328

申请日：1998-11-13

Applicant: Fa-Fu Hu ,  Yu-Chung Hung ,  Chih-Jen Chang

Inventor： Fa-Fu Hu ,  Yu-Chung Hung ,  Chih-Jen Chang

IPC: G01B1100

CPC classification number: G03F9/7084 ,  G03F9/7015

Abstract: A wafer alignment system aligns a wafer by checking the alignment marks formed on the back surface of the wafer. A number of guiding rays are used to determine the corresponding alignment mark on the back of the wafer to ensure that the wafer is properly aligned. The alignment system of the invention also includes a wafer stage and a fixed base, wherein the wafer stage and the fixed base contains a number of apertures that allow the guiding rays to pass through and strike on the alignment marks on the wafer.

Abstract translation: 晶片对准系统通过检查形成在晶片背表面上的对准标记来对准晶片。 使用许多引导光线来确定晶片背面上的相应对准标记，以确保晶片正确对准。 本发明的对准系统还包括晶片台和固定基座，其中晶片台和固定基座包含允许引导光线通过并撞击晶片上的对准标记的多个孔。