公开(公告)号：US07939390B2

公开(公告)日：2011-05-10

申请号：US12765979

申请日：2010-04-23

Applicant: Stephen P. Ayotte ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Stephen P. Ayotte ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H01L21/338 ,  H01L21/8244

CPC classification number: H01L23/5223 ,  H01L22/34 ,  H01L24/02 ,  H01L24/11 ,  H01L28/60 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/29116 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30105 ,  Y10S438/957 ,  H01L2924/00

Abstract: A semiconductor structure formation method and operation method. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.

Abstract translation: 一种半导体结构的形成方法和操作方法。 该结构包括（i）电介质层，（ii）电介质层上的底部电容器板和导电线，（iii）底部电容器板顶部的顶部电容器板，（iv）间隙区域，以及 （v）电介质层上的焊球。 电介质层包括限定垂直于顶表面的参考方向的顶表面。 顶部电容器板在底部电容器板上沿参考方向重叠。 间隙区域夹在底部电容器板和顶部电容器板之间。 间隙区域不包括任何液体或固体材料。 焊球与导电线电连接。 顶部电容器板设置在电介质层和焊球之间。

公开(公告)号：US07935408B2

公开(公告)日：2011-05-03

申请号：US11924662

申请日：2007-10-26

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: B32B3/10 ,  B05D5/12 ,  H01L23/485

CPC classification number: H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/14136 ,  H01L2224/26152 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10S428/901 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/4921 ,  Y10T29/49222 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24347 ,  Y10T428/24479 ,  Y10T428/24529 ,  Y10T428/24545 ,  Y10T428/24612 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, first dielectric layer, an underfill layer, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The underfill layer is formed over the top surface of the first dielectric layer and within the first opening. The second substrate is formed over and in contact with the underfill layer.

Abstract translation: 一种电气结构和成型方法。 电结构包括第一衬底，第一介电层，底部填充层和第二衬底。 第一介电层形成在第一基板的顶表面上。 第一电介质层包括延伸穿过所述第一电介质层的顶表面和底表面的第一开口。 底部填充层形成在第一介电层的顶表面上并且在第一开口内。 第二衬底形成在底部填充层上并与底部填充层接触。

公开(公告)号：US07863734B2

公开(公告)日：2011-01-04

申请号：US12186655

申请日：2008-08-06

Applicant: Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

Inventor： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

IPC: H01L23/34 ,  H01L23/48

CPC classification number: H01L24/10 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10674 ,  Y10T436/171538 ,  Y10T436/172307 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.

Abstract translation: 一种电子装置和包装电子装置的方法。 该装置包括：第一基板，第二基板和具有第一侧和相对的第二侧的集成电路芯片，在第一侧上的第一组芯片焊盘和在集成的第二侧上的第二组芯片焊盘 电路芯片，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的对应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。

公开(公告)号：US07862987B2

公开(公告)日：2011-01-04

申请号：US11942753

申请日：2007-11-20

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: G03F7/26

CPC classification number: H01L21/0272 ,  G03F7/095 ,  G03F7/168 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01047

Abstract: An electrical structure and method of forming. The method comprises providing a substrate structure. A first layer comprising a first photosensitive material having a first polarity is formed over and in contact with the substrate structure. A second layer comprising photosensitive material having a second polarity is formed over and in contact with the first layer. The first polarity comprises an opposite polarity as the second polarity. Portions of the first and second layers are simultaneously exposed to a photo exposure light source. The portions of the first and second layers are developed such that structures are formed.

Abstract translation: 一种电气结构和成型方法。 该方法包括提供衬底结构。 包括具有第一极性的第一感光材料的第一层形成在衬底结构上并与衬底结构接触。 包含具有第二极性的感光材料的第二层形成在第一层之上并与第一层接触。 第一极性包括与第二极性相反的极性。 第一层和第二层的一部分同时暴露于曝光光源。 第一层和第二层的部分被显影以形成结构。

公开(公告)号：US07459785B2

公开(公告)日：2008-12-02

申请号：US11941165

申请日：2007-11-16

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H01L23/52 ,  H01L23/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/11912 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2224/05552

Abstract: An electrical interconnection structure. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.

Abstract translation: 电互连结构。 该电气结构包括一个衬底，该衬底包括导电焊盘和该衬底上的第一介电层和该导电焊盘。 第一介电层包括通孔。 金属层形成在第一介电层之上和通孔内。 第二电介质层形成在金属层上。 在通孔内形成球限制金属化层。 在球限制金属化层的表面上形成光致抗蚀剂层。 在光致抗蚀剂层的第一开口内形成第一焊球，在光致抗蚀剂层的第二开口内形成第二焊球。

公开(公告)号：US09105465B2

公开(公告)日：2015-08-11

申请号：US13053803

申请日：2011-03-22

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

IPC: H01L29/02 ,  H01L21/02

CPC classification number: H01L21/02021

Abstract: The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.

Abstract translation: 本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。 提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。 该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。 该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。 有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。

公开(公告)号：US08288747B2

公开(公告)日：2012-10-16

申请号：US12842158

申请日：2010-07-23

Applicant: Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

Inventor： Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

IPC: H01L29/00 ,  H01L47/00

CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

Abstract: A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.

Abstract translation: 一个结构。 该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。 电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。 电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

公开(公告)号：US07547576B2

公开(公告)日：2009-06-16

申请号：US11275867

申请日：2006-02-01

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H01L21/00

CPC classification number: H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.

Abstract translation: 其形成结构及其方法。 半导体结构包括与第一半导体芯片直接物理接触的第一半导体芯片和N个焊料凸块，其中N是正整数。 半导体结构还包括在第一半导体芯片的周边上的第一焊料壁，使得第一焊料壁形成围绕N个焊料凸点的闭环。

公开(公告)号：US07462509B2

公开(公告)日：2008-12-09

申请号：US11383595

申请日：2006-05-16

Applicant: Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

Inventor： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L24/10 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10674 ,  Y10T436/171538 ,  Y10T436/172307 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An method of packaging an electronic device. The method for packaging the device including: providing a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.

Abstract translation: 一种封装电子设备的方法。 用于封装器件的方法包括：提供第一衬底，第二衬底和具有第一侧和相对第二侧的集成电路芯片，第一组芯片焊盘和第二组芯片焊盘， 集成电路芯片的第二侧，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的相应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。

公开(公告)号：US07348210B2

公开(公告)日：2008-03-25

申请号：US10908084

申请日：2005-04-27

Applicant: Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Juris Sprogis

Inventor： Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Juris Sprogis

IPC: H01L21/00

CPC classification number: H01L23/556 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.

Abstract translation: 一种结构及其形成方法。 该方法包括（a）提供一种结构，其包括（i）电介质层，（ii）与电介质层顶表面直接物理接触的导电接合焊盘，（iii）介电层上的第一钝化层 其中所述第一钝化层包括位于所述导电接合焊盘正上方的第一孔，以及（iv）填充所述第一孔并电耦合到所述导电接合焊盘的导电焊料凸块; 以及（b）在所述第一钝化层上形成第二钝化层，其中第二钝化层与所述导电焊料凸块直接物理接触，并且其中所述导电焊料凸点在所述第二钝化层形成所述第二钝化层之后立即暴露于周围环境 执行钝化层。