公开(公告)号：US07326860B2

公开(公告)日：2008-02-05

申请号：US11446669

申请日：2006-06-05

Applicant: Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Gary Taylor ,  David Quint

Inventor： Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Gary Taylor ,  David Quint

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01L23/5384 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/0979 ,  H01L2924/00

Abstract: A multilayer substrate having a bonding surface is disclosed. One embodiment of the substrate may comprise a bypass capacitor connection pad disposed on the bonding surface. The bypass capacitor connection pad may have a bypass capacitor power pad and a bypass capacitor ground pad. The substrate may also comprise a plurality of power vias routed from the bypass capacitor power pad to a first redistribution layer spaced apart from the bonding surface and a plurality of ground vias routed from the bypass capacitor ground pad to the first redistribution layer. The substrate may further comprise a plurality of power and ground vias routed from the first redistribution layer to a second redistribution layer according to a power and ground via pattern array, wherein the plurality of ground vias are jogged at the first redistribution layer to the plurality of power vias to form the power and ground via pattern array.

Abstract translation: 公开了具有接合面的多层基板。 衬底的一个实施例可以包括设置在接合表面上的旁路电容器连接焊盘。 旁路电容连接焊盘可能具有旁路电容器功率垫和旁路电容接地垫。 衬底还可以包括从旁路电容器功率焊盘路由到与接合表面间隔开的第一再分配层的多个电源通孔和从旁路电容器接地焊盘路由到第一再分配层的多个接地通孔。 衬底还可以包括根据功率和接地经由图案阵列从第一再分配层路由到第二再分布层的多个电源和接地通孔，其中多个接地通孔在第一再分配层处被点动到多个 电源通孔通过图案阵列形成电源和接地。

公开(公告)号：US07075185B2

公开(公告)日：2006-07-11

申请号：US10940100

申请日：2004-09-14

Applicant: Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Gary Taylor ,  David Quint

Inventor： Jerimy Nelson ,  Mark D. Frank ,  Peter Shaw Moldauer ,  Gary Taylor ,  David Quint

IPC: H01L23/48

CPC classification number: H01L23/5384 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/0979 ,  H01L2924/00

Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Abstract translation: 公开了一种用于从旁路电容器焊盘排列多层衬底中的通孔的方法。 方法的一个实施例可以包括布置在多层基板的第一表面上与旁路电容器接地垫间隔开的旁路电容器功率垫，将多个电源通孔从旁路电容器功率垫路由到与第二再分布层间隔开的第一再分配层 并且将多个接地通孔从旁路电容器接地焊盘路由到第一再分布层。 该方法还可以包括将第一再分配层处的多个接地通孔点动到多个电源通孔以提供电源和接地通孔图案，并将电源和接地通孔从第一再分配层路由到间隔开的第二再分配层 基于通过图案的功率和接地的第一再分配层。

公开(公告)号：US20050223348A1

公开(公告)日：2005-10-06

申请号：US11142999

申请日：2005-06-02

Applicant: Mark Frank ,  Jerimy Nelson ,  David Quint

Inventor： Mark Frank ,  Jerimy Nelson ,  David Quint

IPC: G06F9/45 ,  G06F17/50

CPC classification number: G06F17/5081

Abstract: A method evaluates signal trace discontinuities in an electronic design of the type having one or more traces. The method includes the steps of formulating one or more trace discontinuity rules, processing the electronic design to determine whether the traces violate the trace discontinuity rules, and generating an indicator (e.g., a DRC) associated with the electronic design to identify violated trace discontinuity rules. Each level, each signal net, or a group of signal nets may be evaluated, for example, to ensure compliance with the trace discontinuity rules.

公开(公告)号：US2915227A

公开(公告)日：1959-12-01

申请号：US66106257

申请日：1957-05-23

Applicant: DAVID QUINT

Inventor： DAVID QUINT

IPC: B65D47/24

CPC classification number: B65D47/242