公开(公告)号：US20180242464A1

公开(公告)日：2018-08-23

申请号：US15756745

申请日：2016-08-08

Applicant: DENSO CORPORATION

Inventor： Kenichiro HASEGAWA ,  Tomohiro YOKOCHI ,  Yasunori KASAMA

IPC: H05K3/46 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48227 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/0014 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/09454 ,  H05K2201/09527 ,  H05K2201/09627 ,  H05K2201/09709 ,  H05K2201/09827

Abstract: Before a laminated body is subjected to hot pressing, at least two or more land electrodes are displaced from each other as viewed in the lamination direction, whereby at least two or more gaps disposed in the lamination direction are displaced from each other as viewed in the lamination direction. The hot pressing on the laminated body causes resin materials that compose resin films to flow and fill the gaps in the laminated body. Consequently, the planarity of a multilayer substrate can be improved to a greater extent than in a case where a plurality of gaps disposed in the lamination direction is located at the same position as viewed in the lamination direction.

公开(公告)号：US09763331B2

公开(公告)日：2017-09-12

申请号：US15066244

申请日：2016-03-10

Applicant: FUJITSU LIMITED

Inventor： Yoshiyuki Hiroshima ,  Naoki Nakamura ,  Akiko Matsui ,  Mitsuhiko Sugane ,  Takahide Mukoyama ,  Tetsuro Yamada ,  Kohei Choraku

IPC: H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K3/46

CPC classification number: H05K1/185 ,  H05K1/0216 ,  H05K1/115 ,  H05K1/162 ,  H05K3/306 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09809 ,  H05K2201/10015 ,  H05K2201/10287 ,  H05K2201/10295

Abstract: A printed circuit board includes: a first electrode made of a tubular electric conductor formed on an inner wall of a first hole formed in the printed circuit board; a dielectric body disposed inside the first electrode; and a second electrode made of a tubular electric conductor formed on an inner wall of a second hole extending through the dielectric body, the second electrode having a center axis concentric with the first electrode.

公开(公告)号：US20150228416A1

公开(公告)日：2015-08-13

申请号：US14555633

申请日：2014-11-27

Applicant: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H01G17/00 ,  H05K1/18 ,  H05K1/11 ,  H03H7/01 ,  H01G4/008 ,  H05K1/02 ,  H01F27/28 ,  H05K1/16 ,  H01G4/12

CPC classification number: H01G17/00 ,  H01F27/2804 ,  H01G4/008 ,  H01G4/1209 ,  H01G4/224 ,  H01G4/228 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/97 ,  H01L28/65 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2924/19105 ,  H03H7/0115 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/186 ,  H05K3/005 ,  H05K3/0052 ,  H05K3/4647 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/308

Abstract: A chip socket defined by an organic matrix framework, wherein the organic matrix framework comprises at least one via post layer where at least one via through the framework around the socket includes at least one capacitor comprising a lower electrode, a dielectric layer and an upper electrode in contact with the via post.

Abstract translation: 由有机矩阵框架限定的芯片插座，其中所述有机矩阵框架包括至少一个通孔支柱层，其中穿过所述插座周围的框架的至​​少一个通孔包括至少一个电容器，所述电容器包括下电极，介电层和上电极 与通孔接触。

公开(公告)号：US08861217B2

公开(公告)日：2014-10-14

申请号：US13668692

申请日：2012-11-05

Applicant: Apple Inc.

Inventor： Gloria Lin ,  William Bryson Gardner, Jr. ,  Joseph Fisher, Jr. ,  Dennis Pyper ,  Amir Salehi

IPC: H05K7/20 ,  H01R43/00 ,  H05K1/14 ,  H05K1/11 ,  H05K3/22

CPC classification number: H05K1/145 ,  H05K1/115 ,  H05K1/141 ,  H05K3/222 ,  H05K2201/0919 ,  H05K2201/09627 ,  H05K2201/10446 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: This relates to systems and methods for providing one or more vias through a module of an electrical system. For example, in some embodiments, the module can include one or more passive elements and/or active of the electrical system around which a packaging has been plastic molded. The module can be stacked under another component of the electrical system. Vias can then be provided that extend through the module. The vias can include, for example, electrically conductive pathways. In this manner, the vias can provide electrical pathways for coupling the component stacked on top of the module to other entities of an electronic device including the electrical system. For example, the component can be coupled to other entities such as other components, other modules, printed circuit boards, other electrical systems, or to any other suitable entity.

Abstract translation: 这涉及用于通过电气系统的模块提供一个或多个通孔的系统和方法。 例如，在一些实施例中，模块可以包括电气系统的一个或多个无源元件和/或主动元件，其中包装已经被塑料模制。 该模块可以堆叠在电气系统的另一个部件下。 然后可以提供通过模块延伸的通孔。 通孔可以包括例如导电通路。 以这种方式，通孔可以提供用于将堆叠在模块顶部上的部件耦合到包括电气系统的电子设备的其他实体的电路径。 例如，组件可以耦合到诸如其他组件，其他模块，印刷电路板，其他电气系统或任何其它合适实体的其他实体。

公开(公告)号：US08800143B2

公开(公告)日：2014-08-12

申请号：US13156715

申请日：2011-06-09

Applicant: Youhong Wu

Inventor： Youhong Wu

IPC: H01K3/10

CPC classification number: H05K1/115 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a multi-layer printed wiring board including forming a core substrate, forming a first interlayer insulation layer over the core substrate, forming a first filled via in the first interlayer insulation layer, the first filled via having a bottom portion having a first diameter, forming a second interlayer insulation layer over the first interlayer insulation layer, and forming a second filled via in the second interlayer insulation layer, the second filled via having a bottom portion having a second diameter smaller than the first diameter.

Abstract translation: 一种制造多层印刷布线板的方法，包括形成芯基板，在芯基板上形成第一层间绝缘层，在第一层间绝缘层中形成第一填充通孔，第一填充通孔具有底部， 在所述第一层间绝缘层上形成第二层间绝缘层，在所述第二层间绝缘层中形成第二填充通孔，所述第二填充通孔具有第二直径小于所述第一直径的第二直径。

公开(公告)号：US08674477B2

公开(公告)日：2014-03-18

申请号：US13542444

申请日：2012-07-05

Applicant: Hao Shi ,  Jung-Hoon Chun ,  Xingchao Yuan

Inventor： Hao Shi ,  Jung-Hoon Chun ,  Xingchao Yuan

IPC: H01L27/08

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/645 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/165 ,  H05K3/4602 ,  H05K2201/09627 ,  H05K2201/10674 ,  H01L2924/00

Abstract: In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.

Abstract translation: 在一些实施例中，半导体封装包括具有多个层的衬底，从第一层到最终层，耦合到第一层的管芯，耦合到最终层的焊球等电连接器以及布置在其上的螺旋迹线 并且电连接在管芯和电连接器之间。 选择螺旋迹线的电感，使得封装具有预定的阻抗。 相应地选择材料，横截面积，绕组的数量和密度以及螺旋迹线的总长度。 在其他实施例中，半导体封装包括具有多层的衬底; 耦合到第一层的管芯; 耦合到最终层的电连接器; 以及衬底中或衬底上的螺旋迹线。 螺旋迹线靠近模具，并且电连接在管芯和电连接器之间。

公开(公告)号：US08624297B2

公开(公告)日：2014-01-07

申请号：US12579517

申请日：2009-10-15

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H01L27/10 ,  H01L21/4763

CPC classification number: H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

Abstract: An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

Abstract translation: 集成电路衬底被设计和制造，具有选择性地施加的传输线参考平面金属层，以实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输线参考平面金属层之间的电容引起的阻抗下降。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

公开(公告)号：US08604357B2

公开(公告)日：2013-12-10

申请号：US12501044

申请日：2009-07-10

Applicant: Tsutomu Takeda

Inventor： Tsutomu Takeda

IPC: H05K3/42 ,  H05K3/30 ,  H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0237 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09645 ,  H05K2201/09809 ,  H05K2203/0242 ,  H05K2203/175

Abstract: A wiring board has a plurality of wiring layers, a first land, a second land, a first via and a second via. The first land and the second land are formed on at least one wiring layer of the wiring board and are disposed to partially overlap with each other. The first via and the second via are formed in association with the first land and the second land, respectively. The first via and the second via electrically connect a first wiring layer and a second wiring layer of the plurality of wiring layers to each other. The wiring board has a separator that is formed by a hole that separates the first land and the second land from each other.

Abstract translation: 布线板具有多个布线层，第一片，第二片，第一片和第二片。 第一焊盘和第二焊盘形成在布线板的至少一个布线层上并且彼此部分地重叠。 第一通孔和第二通孔分别与第一焊盘和第二焊盘相关联地形成。 第一通孔和第二通孔将多个布线层中的第一布线层和第二布线层彼此电连接。 布线板具有由将第一焊盘和第二焊盘彼此分隔开的孔形成的隔板。

公开(公告)号：US08390308B2

公开(公告)日：2013-03-05

申请号：US12039854

申请日：2008-02-29

Applicant: Michael Carney ,  Marek Reksnis ,  Ted Toth

Inventor： Michael Carney ,  Marek Reksnis ,  Ted Toth

IPC: G01R31/00

CPC classification number: H05K1/116 ,  G01R1/07314 ,  G01R3/00 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/09627 ,  H05K2201/10303 ,  Y10T29/49124

Abstract: There is disclosed an electronic testbed, an electronic testbed board, and a method for positioning receptacles for nails in the electronic testbed board. In an embodiment, the electronic testbed board includes a mounting through-hole for mounting a receptacle for a nail. The mounting through-hole is drilled to a suitably precise diameter for mounting the receptacle substantially perpendicular to the testbed board. One or more via-holes are located adjacent the mounting through-hole, and are adapted to allow an electrical connection between any conductive layers provided at the one or more via-holes. The receptacle may be mounted more accurately and the electronic test bed may be built more accurately by separating the functions of the via-holes and the mounting through-hole.

Abstract translation: 公开了一种电子测试台，电子测试台和用于在电子测试台中定位钉子的插座的方法。 在一个实施例中，电子测试台板包括用于安装用于钉子的插座的安装通孔。 将安装通孔钻入适当精确的直径，以将基座垂直于测试台板安装。 一个或多个通孔位于安装通孔附近，并且适于允许在一个或多个通孔处提供的任何导电层之间的电连接。 可以更准确地安装插座，并且可以通过分离通孔和安装通孔的功能来更准确地构建电子测试台。

公开(公告)号：US08379403B2

公开(公告)日：2013-02-19

申请号：US12750458

申请日：2010-03-30

Applicant: David W. Waite ,  James L. Blair ,  Ashish Lohiya ,  Arvid G. Sammuli ,  Jeffrey T. Smith ,  Saritha Narra

Inventor： David W. Waite ,  James L. Blair ,  Ashish Lohiya ,  Arvid G. Sammuli ,  Jeffrey T. Smith ,  Saritha Narra

IPC: H05K7/00

CPC classification number: H05K1/144 ,  G01R1/06772 ,  G01R31/2822 ,  H01R12/52 ,  H01R13/2414 ,  H05K1/0222 ,  H05K1/145 ,  H05K3/325 ,  H05K2201/0314 ,  H05K2201/09618 ,  H05K2201/09627 ,  H05K2201/10378 ,  H05K2201/2009 ,  H05K2201/2036 ,  H05K2203/162

Abstract: A spacer-connector and connection arrangements between daughter boards and motherboards are disclosed. Assemblies may include a daughter board one or more spacer-connectors spacing the daughter board above a motherboard and conductive elastomers providing electrical connections between the daughter board and spacer-connector and between the spacer-connector and the motherboard. The spacer-connector may include ground, power, digital and/or controlled impedance RF pathways to conduct signals between the daughter board to the mother board.

Abstract translation: 公开了间隔器连接器和子板和母板之间的连接布置。 组件可以包括子板，一个或多个间隔器 - 连接器将母板间隔开在母板上方，并且导电弹性体提供子板和间隔器连接器之间以及间隔物连接器和母板之间的电连接。 间隔器连接器可以包括接地，功率，数字和/或控制的阻抗RF路径，以在子板到母板之间传导信号。