公开(公告)号：US20060154429A1

公开(公告)日：2006-07-13

申请号：US11031142

申请日：2005-01-07

Applicant: Joel de Souza ,  Keith Fogel ,  John Ott ,  Devendra Sadana ,  Katherine Saenger

Inventor： Joel de Souza ,  Keith Fogel ,  John Ott ,  Devendra Sadana ,  Katherine Saenger

IPC: H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/2022

Abstract: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.

Abstract translation: 本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向 具有不同的方向。 更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶 非晶层的原始方向。 本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。 本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

公开(公告)号：US20060081837A1

公开(公告)日：2006-04-20

申请号：US11293774

申请日：2005-12-02

Applicant: Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Effendi Leobandung ,  Devendra Sadana

Inventor： Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Effendi Leobandung ,  Devendra Sadana

IPC: H01L31/109

CPC classification number: H01L29/78696 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/76251 ,  H01L29/7842

Abstract: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

公开(公告)号：US20050148162A1

公开(公告)日：2005-07-07

申请号：US10751207

申请日：2004-01-02

Applicant: Huajie Chen ,  Dan Mocuta ,  Richard Murphy ,  Stephen Bedell ,  Devendra Sadana

Inventor： Huajie Chen ,  Dan Mocuta ,  Richard Murphy ,  Stephen Bedell ,  Devendra Sadana

IPC: C30B25/02 ,  C30B29/52 ,  H01L21/20 ,  H01L21/205 ,  H01L21/306 ,  H01L21/36 ,  H01L21/44

CPC classification number: H01L21/02046 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02661

Abstract: The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves only a sub-monolayer of oxygen (typically 1×1013-1×1015/cm2 of oxygen) at the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process in a chlorine containing environment which heats the silicon germanium, strained silicon, or thin silicon-on-insulator surface sufficiently to remove the remaining oxygen from the surface. By introducing a small amount of chlorine containing gases, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.

Abstract translation: 本发明在硅​​锗，图案化的应变硅或图案化的绝缘体上硅表面上形成外延含硅层，并避免产生外延含硅层生长的粗糙表面。 为了避免产生粗糙表面，本发明首先对硅锗，图案化应变硅或图案化的绝缘体上硅表面进行氢氟酸蚀刻工艺。 该蚀刻工艺从表面除去大部分氧化物，并且仅留下氧气的亚单层（通常为1×10 13/1×10 15 / cm 2以上） 的氧），图案化的应变硅或图案化的绝缘体上硅表面。 然后，本发明在含氯环境中进行氢预烘烤过程，其中充分加热硅锗，应变硅或薄的绝缘体上硅表面以从表面除去剩余的氧。 通过引入少量的含氯气体，加热过程避免改变硅锗，图案化的应变硅或图案化的绝缘体上硅表面的粗糙度。 然后进行外延生长硅锗，图案化应变硅或图案化硅绝缘体表面上的外延硅含量层的工艺。

公开(公告)号：US20050093100A1

公开(公告)日：2005-05-05

申请号：US10700085

申请日：2003-11-03

Applicant: Tze-chiang Chen ,  Guy Cohen ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

Inventor： Tze-chiang Chen ,  Guy Cohen ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC: H01L21/762 ,  H01L27/12 ,  H01L27/144 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18 ,  H01L31/117

CPC classification number: H01L21/76254 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1812 ,  Y02E10/547

Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

Abstract translation: 提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。 在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

公开(公告)号：US20050067055A1

公开(公告)日：2005-03-31

申请号：US10674647

申请日：2003-09-30

Applicant: Kwang Choe ,  Keith Fogel ,  Siegfried Maurer ,  Ryan Mitchell ,  Devendra Sadana

Inventor： Kwang Choe ,  Keith Fogel ,  Siegfried Maurer ,  Ryan Mitchell ,  Devendra Sadana

IPC: H01L21/265 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/762 ,  C23C8/36

CPC classification number: H01L21/76243 ,  H01L21/26533 ,  H01L21/3063 ,  H01L21/31662

Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

Abstract translation: 提供了一种制造在含Si的上层下方具有薄但均匀的掩埋氧化物区域的硅绝缘体（SOI）的方法。 通过首先修饰含Si衬底的表面以包含大量的空位或空隙的浓度来制造SOI结构。 接下来，含硅层通常但不总是形成在衬底顶上，然后使用低氧剂量将氧离子注入到结构中。 然后将结构退火以将注入的氧离子转化成薄但均匀的热掩埋氧化物区域。

公开(公告)号：US20050048778A1

公开(公告)日：2005-03-03

申请号：US10654232

申请日：2003-09-03

Applicant: Stephen Bedell ,  Huajie Chen ,  Keith Fogel ,  Devendra Sadana

Inventor： Stephen Bedell ,  Huajie Chen ,  Keith Fogel ,  Devendra Sadana

IPC: H01L29/161 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04 ,  C30B1/00 ,  C30B3/00 ,  C30B5/00 ,  C30B28/02 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/7624 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/24917

Abstract: High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

Abstract translation: 在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化 温度。 因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。

公开(公告)号：US06177289B1

公开(公告)日：2001-01-23

申请号：US09205433

申请日：1998-12-04

Applicant: John Crow ,  Steve Koester ,  Daniel M. Kuchta ,  Dennis L. Rogers ,  Devendra Sadana ,  Sandip Tiwari

Inventor： John Crow ,  Steve Koester ,  Daniel M. Kuchta ,  Dennis L. Rogers ,  Devendra Sadana ,  Sandip Tiwari

IPC: H01L2166

CPC classification number: H01L31/03529 ,  H01L31/035281 ,  H01L31/105 ,  Y02E10/50

Abstract: A monolithic semiconductor optical detector is formed on a substrate having a plurality of substantially parallel trenches etched therein. The trenches are further formed as a plurality of alternating N-type and P-type trench regions separated by pillar regions of the substrate which operate as an I region between the N and P trench regions. First and second contacts are formed on the surface of the substrate and interconnect the N-type trench regions and the P-type trench regions, respectively. Preferably, the trenches are etched with a depth comparable to an optical extinction length of optical radiation to which the detector is responsive.

Abstract translation: 单片半导体光检测器形成在其上蚀刻有多个基本上平行的沟槽的衬底上。 沟槽还形成为由作为N沟道区域和P沟道区域之间的I区域的基板的柱状区域分离的多个交替的N型和P型沟槽区域。 第一和第二触点形成在衬底的表面上并分别互连N型沟槽区和P型沟槽区。 优选地，以与检测器响应的光辐射的光消光长度相当的深度蚀刻沟槽。

公开(公告)号：US20120217622A1

公开(公告)日：2012-08-30

申请号：US13467537

申请日：2012-05-09

Applicant: Stephen W. Bedell ,  Devendra Sadana ,  Keith E. Fogel ,  David Fried ,  Paul A. Lauro

Inventor： Stephen W. Bedell ,  Devendra Sadana ,  Keith E. Fogel ,  David Fried ,  Paul A. Lauro

IPC: H01L29/02 ,  H01L21/78

CPC classification number: H01L23/585 ,  H01L21/304 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Imparting a controlled amount of stress in an assembly comprising a semiconductor circuit on a substrate comprises depositing a tensile stressed metal film stressor layer onto the surface of the circuit. Establishing a fracture region below electrically active regions of the circuit, adhering a foil handle to the assembly and pulling it away from the assembly induces mechanical fracture in the fracture region below the electrically active regions. The mechanical fracture propagates parallel and laterally to the surface of the substrate and below the circuit to produce a thin flexible circuit on a residual substrate. The circuit is under compressive strain that is changed by modifying the stressor layer or residual substrate. Individualized circuits or a circuit may also be defined above the fracture by dividing the circuit into preselected regions with surrounding trenches before fracture. We harvest the circuit(s) by pulling the foil handle away from the assembly.

Abstract translation: 在包括衬底上的半导体电路的组件中施加受控量的应力包括将拉应力金属膜应力层沉积到电路的表面上。 在电路的电活性区域之下建立断裂区域，将箔手柄粘附到组件并将其从组件拉出，从而在电活性区域下方的断裂区域中引起机械断裂。 机械断裂平行且横向地传播到基板的表面并在电路下面，以在残留的基板上产生薄的柔性电路。 电路处于压应变状态，通过改变应力层或残留衬底而改变。 在断裂之前，也可以将断路中的电路划分成具有周围沟槽的预定区域，将个体化电路或电路定义在断裂之上。 我们通过将铝箔手柄拉离组件来收集电路。

公开(公告)号：US08247261B2

公开(公告)日：2012-08-21

申请号：US12784688

申请日：2010-05-21

Applicant: Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra Sadana

Inventor： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra Sadana

IPC: H01L21/463

CPC classification number: H01L31/0304 ,  H01L21/20 ,  H01L21/76254 ,  H01L31/03762 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  H01L31/20 ,  Y02E10/548

Abstract: A method for manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. In one embodiment the stress layer comprises a flexible material.

Abstract translation: 一种制造薄膜直接带隙半导体活性太阳能电池器件的方法，包括：提供具有表面的源极衬底，并在表面上设置应力层，该应力层具有与源极衬底表面接触并结合的应力层表面积。 将手柄箔与应力层操作地相关联并且向手柄箔施加力将应力层与源衬底分离，并将源衬底的一部分留在应力层表面上，基本上对应于与表面相接触的区域 源底物。 该部分的厚度不如源层厚。 应力层厚度低于导致源底材自发剥落的厚度。 源极衬底可以包括无机单晶或多晶材料，例如Si，Ge，GaAs，SiC，蓝宝石或GaN。 在一个实施例中，应力层包括柔性材料。

公开(公告)号：US20110147809A1

公开(公告)日：2011-06-23

申请号：US12644092

申请日：2009-12-22

Applicant: Bin Yang ,  Devendra Sadana ,  Christian Lavoie ,  Ahmet Ozcan

Inventor： Bin Yang ,  Devendra Sadana ,  Christian Lavoie ,  Ahmet Ozcan

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method includes forming a silicon germanium layer, forming a layer comprising carbon and silicon on a top surface of the silicon germanium layer, forming a metal layer above the layer comprising carbon and silicon, and performing a thermal treatment to convert at least the layer comprising carbon and silicon to form a metal silicide layer.

Abstract translation: 一种方法包括形成硅锗层，在硅锗层的顶表面上形成包含碳和硅的层，在包含碳和硅的层之上形成金属层，并进行热处理以至少将含有 碳和硅以形成金属硅化物层。