公开(公告)号：US08633097B2

公开(公告)日：2014-01-21

申请号：US12713572

申请日：2010-02-26

Applicant: Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi ,  Brent A. Wacaser

Inventor： Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi ,  Brent A. Wacaser

IPC: H01L21/22 ,  H01L21/38 ,  H01L21/385

CPC classification number: H01L31/0304 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/548

Abstract: A method for forming a single-junction photovoltaic cell includes forming a dopant layer on a surface of a semiconductor substrate; diffusing the dopant layer into the semiconductor substrate to form a doped layer of the semiconductor substrate; forming a metal layer over the doped layer, wherein a tensile stress in the metal layer is configured to cause a fracture in the semiconductor substrate; removing a semiconductor layer from the semiconductor substrate at the fracture; and forming the single junction photovoltaic cell using the semiconductor layer. A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer.

Abstract translation: 一种形成单结光伏电池的方法包括在半导体衬底的表面上形成掺杂剂层; 将掺杂剂层扩散到半导体衬底中以形成半导体衬底的掺杂层; 在所述掺杂层上形成金属层，其中所述金属层中的拉伸应力构造成在所述半导体衬底中引起断裂; 在断裂时从半导体衬底去除半导体层; 以及使用半导体层形成单结光伏电池。 单结光伏电池包括掺杂剂，该掺杂层包含扩散到半导体衬底中的掺杂剂; 形成在掺杂层上的图案化导电层; 半导体层，其包括位于掺杂层的与图案化导电层相对的表面上的掺杂层上的半导体衬底; 以及形成在半导体层上的欧姆接触层。

公开(公告)号：US20130000707A1

公开(公告)日：2013-01-03

申请号：US13614946

申请日：2012-09-13

Applicant: Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi

Inventor： Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi

IPC: H01L31/06

CPC classification number: H01L31/0735 ,  H01L21/02002 ,  H01L31/0304 ,  H01L31/03046 ,  H01L31/0725 ,  H01L31/1808 ,  H01L31/184 ,  H01L31/1844 ,  H01L31/1892 ,  Y02E10/544 ,  Y02P70/521

Abstract: A method for fabrication of a multijunction photovoltaic (PV) cell includes forming a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the largest bandgap being located on the substrate to the junction having the smallest bandgap being located on top of the stack; forming a metal layer, the metal layer having a tensile stress, on top of the junction having the smallest bandgap; adhering a flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the metal layer.

Abstract translation: 一种制造多结光伏（PV）电池的方法包括在衬底上形成包括多个结的叠层，所述多个结中的每一个具有相应的带隙，其中所述多个结从具有最大带隙的结点排序 位于具有最小带隙位于堆叠顶部的基底上的基底上; 在具有最小带隙的结的顶部上形成具有拉伸应力的金属层; 将柔性基板粘附到金属层上; 并且在基板的断裂处从基板剥离半导体层，其中响应于金属层中的拉伸应力而形成断裂。

公开(公告)号：US20100311250A1

公开(公告)日：2010-12-09

申请号：US12784688

申请日：2010-05-21

Applicant: Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra Sadana

Inventor： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra Sadana

IPC: H01L21/30

CPC classification number: H01L31/0304 ,  H01L21/20 ,  H01L21/76254 ,  H01L31/03762 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  H01L31/20 ,  Y02E10/548

Abstract: A method for manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. In one embodiment the stress layer comprises a flexible material.

Abstract translation: 一种制造薄膜直接带隙半导体活性太阳能电池器件的方法，包括提供具有表面的源极衬底，并且在表面上设置应力层，该应力层具有与源极衬底的表面接触并且结合到源极衬底的表面。 将手柄箔与应力层操作地相关联并且向手柄箔施加力将应力层与源衬底分离，并将源衬底的一部分留在应力层表面上，基本上对应于与表面相接触的区域 源底物。 该部分的厚度不如源层厚。 应力层厚度低于导致源底材自发剥落的厚度。 源极衬底可以包括无机单晶或多晶材料，例如Si，Ge，GaAs，SiC，蓝宝石或GaN。 在一个实施例中，应力层包括柔性材料。

公开(公告)号：US20080206965A1

公开(公告)日：2008-08-28

申请号：US11679308

申请日：2007-02-27

Applicant: Oleg Gluschenkov ,  Yaocheng Liu ,  Alexander Reznicek ,  Devendra Sadana

Inventor： Oleg Gluschenkov ,  Yaocheng Liu ,  Alexander Reznicek ,  Devendra Sadana

IPC: H01L21/20

CPC classification number: H01L29/4983 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02667 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Disclosed herein is a method of preparing strained silicon comprising annealing a carbon-doped silicon-germanium (SiGe:C) alloy containing region disposed adjacent to a silicon region, wherein the lattice constant of the SiGe:C alloy after annealing is greater than that of the SiGe:C alloy prior to annealing. The method can be used to prepare articles including metal oxide semiconductor field effect transistor (MOSFET) devices.

Abstract translation: 本发明公开了一种制备应变硅的方法，包括退火邻近硅区的碳掺杂硅 - 锗（SiGe：C）合金含有区域，其中退火后SiGe：C合金的晶格常数大于 退火之前的SiGe：C合金。 该方法可用于制备包括金属氧化物半导体场效应晶体管（MOSFET）器件的制品。

公开(公告)号：US20080050887A1

公开(公告)日：2008-02-28

申请号：US11924207

申请日：2007-10-25

Applicant: Tze-chiang Chen ,  Guy Cohen ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

Inventor： Tze-chiang Chen ,  Guy Cohen ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC: H01L21/30

CPC classification number: H01L21/76254 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1812 ,  Y02E10/547

Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

Abstract translation: 提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。 在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

公开(公告)号：US20070281439A1

公开(公告)日：2007-12-06

申请号：US11840389

申请日：2007-08-17

Applicant: Stephen Bedell ,  Keith Fogel ,  Bruce Furman ,  Sampath Purushothaman ,  Devendra Sadana ,  Anna Topol

Inventor： Stephen Bedell ,  Keith Fogel ,  Bruce Furman ,  Sampath Purushothaman ,  Devendra Sadana ,  Anna Topol

IPC: H01L21/30 ,  H01L21/00

CPC classification number: H01L21/76259 ,  Y10T428/249961

Abstract: Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a thee dimensional integrated structure is provided.

Abstract translation: 提供了制造半导体器件的技术。 一方面，提供了层转移结构。 层转移结构包括具有调谐孔隙度的多孔区域的载体衬底以及限定分离平面的注入物质的组合。另一方面，提供了一种形成层转移结构的方法。 另一方面，提供了一种形成一维一体结构的方法。

公开(公告)号：US20070164356A1

公开(公告)日：2007-07-19

申请号：US11332564

申请日：2006-01-13

Applicant: Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

Inventor： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

Abstract translation: 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

公开(公告)号：US20060275961A1

公开(公告)日：2006-12-07

申请号：US11492271

申请日：2006-07-25

Applicant: Kevin Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra Sadana ,  Leathen Shi ,  Min Yang

Inventor： Kevin Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra Sadana ,  Leathen Shi ,  Min Yang

IPC: H01L21/84

CPC classification number: H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

Abstract translation: 提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。 在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。 根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。 该方法提供混合基板，其中至少一个器件层包括应变Si。

公开(公告)号：US20060244068A1

公开(公告)日：2006-11-02

申请号：US11116053

申请日：2005-04-27

Applicant: Joel Desouza ,  Devendra Sadana ,  Katherine Saenger ,  Chun-yung Sung ,  Min Yang ,  Haizhou Yin

Inventor： Joel Desouza ,  Devendra Sadana ,  Katherine Saenger ,  Chun-yung Sung ,  Min Yang ,  Haizhou Yin

IPC: H01L27/12

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

Abstract translation: 混合定向衬底允许制造互补金属氧化物半导体（CMOS）电路，其中n型场效应晶体管（nFET）以优选的电子迁移率的半导体取向设置，并且p型场效应晶体管（pFET） 以半导体方向设置，其对于空穴迁移率是最佳的。 本发明公开了完全形成在最佳半导体取向中的FET的性能优点可以通过仅需要将器件的沟道设置在具有最佳取向的半导体中来实现。 描述了各种新的FET结构，其特征在于，至少部分FET通道的FET的源极和/或漏极的至少一部分具有不同的取向。 可以并入其中可并入这些新的FET的混合基板及其制造方法。

公开(公告)号：US20060172505A1

公开(公告)日：2006-08-03

申请号：US11046912

申请日：2005-01-31

Applicant: Steven Koester ,  Devendra Sadana ,  Ghavam Shahidi

Inventor： Steven Koester ,  Devendra Sadana ,  Ghavam Shahidi

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L21/823807 ,  H01L21/02002 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/1203

Abstract: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.

Abstract translation: 制造半导体衬底的方法包括在化合物半导体衬底上外延生长元素半导体层。 绝缘层沉积在元素半导体层的顶部上，以形成第一衬底。 第一衬底被晶片结合到单晶Si衬底上，使得绝缘层与单晶Si衬底结合。 半导体器件包括单晶衬底和形成在单晶衬底上的电介质层。 在介电层上形成半导体化合物，在半导体化合物附近形成与半导体化合物晶格匹配的元素半导体材料。