公开(公告)号：US06927589B2

公开(公告)日：2005-08-09

申请号：US10218379

申请日：2002-08-13

Applicant: James M. Wark

Inventor： James M. Wark

IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28 ,  H05K3/32 ,  H05K3/40 ,  G01R31/02

CPC classification number: G01R1/07307 ,  G01R1/0483 ,  G01R31/2831 ,  G01R31/2886 ,  H05K3/325 ,  H05K3/4007

Abstract: An apparatus for testing unpackaged semiconductor dice having raised ball contact locations is disclosed. The apparatus uses a temporary interconnect wafer that is adapted to establish an electrical connection with the raised ball contact locations on the die without damage to the ball contact locations. The interconnect is fabricated on a substrate, such as silicon, where contact members are formed in a pattern that matches the size and spacing of the ball contact locations on the die to be tested. The contact members on the interconnect wafer are formed as either pits, troughs, or spike contacts. The spike contacts penetrate through the oxide layer formed on the raised ball contact locations. Conductive traces are provided in both rows and columns and are terminated on the inner edges of the walls of the pits formed in the substrate.

Abstract translation: 公开了一种用于测试具有凸起的球接触位置的未包装半导体晶片的测试装置。 该装置使用临时互连晶片，该临时互连晶片适于与模具上的凸起的球接触位置建立电连接，而不会损坏球接触位置。 互连制造在诸如硅的衬底上，其中接触构件以与待测试的管芯上的球接触位置的尺寸和间距匹配的图案形成。 互连晶片上的接触构件形成为凹坑，凹槽或尖峰触点。 尖钉触点穿过形成在凸起接触位置上的氧化物层。 导电迹线设置在行和列中，并且终止于形成在基板中的凹坑的壁的内边缘。

公开(公告)号：US06730526B2

公开(公告)日：2004-05-04

申请号：US10033234

申请日：2001-12-28

Applicant: Salman Akram ,  David R. Hembree ,  James M. Wark

Inventor： Salman Akram ,  David R. Hembree ,  James M. Wark

IPC: H01L2100

CPC classification number: H01L23/5382 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00

Abstract: Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.

Abstract translation: 多芯片模块系统及其制造方法，其中将多芯片模块（MCM）的故障芯片的等同物添加到先前用适当的电连接构造的空位中的模块中。 各种不同的骰子可以通过适配器连接到MCM的相同空位，其中每个适配器具有相同的占位面积，但是不同的适配器能够容纳不同数量和类型的骰子。

公开(公告)号：US06617684B2

公开(公告)日：2003-09-09

申请号：US10232782

申请日：2002-08-28

Applicant: Salman Akram ,  James M. Wark

Inventor： Salman Akram ,  James M. Wark

IPC: H01L2334

CPC classification number: H01L24/85 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/42 ,  H01L23/4334 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/83951 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00011 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of the opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface of the semiconductor chip.

Abstract translation: 一种通过在其上放置形成球顶部的一部分的散热材料在半导体芯片的上表面上提供散热器的装置和方法。 该装置包括附接到衬底并与衬底电连通的半导体芯片。 将阻挡球顶部材料施加到与附接到基板的表面相对的表面（“相对表面”）上的半导体芯片的边缘上，以形成围绕半导体芯片的相对表面的周边的壁，其中阻挡球顶部 材料也延伸到接触并粘附到基底上。 围绕半导体芯片的相对表面的周边的壁形成凹部。 散热球形材料设置在凹部内以接触半导体芯片的相对表面。

公开(公告)号：US06544461B1

公开(公告)日：2003-04-08

申请号：US09677555

申请日：2000-10-02

Applicant: David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

Inventor： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

IPC: B29C4502

CPC classification number: G01R1/0483

Abstract: A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects. A gasket may be used to protect the interconnect contacts during the molding step.

Abstract translation: 提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。 载体包括模制塑料基底，引线框架和互连件。 互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。 通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。 替代实施例的载体包括多个互连件模制或层压的板。 另外，夹子构件保持电路板上与组件电连通的组件。 可以在模制步骤期间使用垫圈来保护互连触点。

公开(公告)号：US06399416B1

公开(公告)日：2002-06-04

申请号：US09642134

申请日：2000-08-18

Applicant: James M. Wark

Inventor： James M. Wark

IPC: H01L2144

CPC classification number: H01L24/85 ,  G11C5/04 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10T29/49004 ,  Y10T29/49144 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

公开(公告)号：US06398043B1

公开(公告)日：2002-06-04

申请号：US09873834

申请日：2001-06-04

Applicant: James M. Wark ,  Michael J. Bettinger

Inventor： James M. Wark ,  Michael J. Bettinger

IPC: A47G1908

CPC classification number: H05K13/0069 ,  Y10S269/90 ,  Y10S269/903 ,  Y10T29/49128

Abstract: A circuit board carrier and method of using the same. The carrier allows circuit boards to be processed on lead frame-based semiconductor processing equipment. The circuit board carrier contains a structure to secure a circuit board thereto and the carrier is sized and shaped, and provided with standardized indexing holes, to allow processing of circuit boards on processing equipment configured for lead frame-based processing.

Abstract translation: 一种电路板载体及其使用方法。 载体允许在基于引线框架的半导体处理设备上处理电路板。 电路板载体包含用于将电路板固定到其上的结构，并且载体的尺寸和形状设置有标准化的分度孔，以允许对配置为基于引线框架的处理的处理设备上的电路板进行处理。

公开(公告)号：US06253758B1

公开(公告)日：2001-07-03

申请号：US09619942

申请日：2000-07-20

Applicant: James M. Wark ,  Salman Akram

Inventor： James M. Wark ,  Salman Akram

IPC: B28D704

CPC classification number: B28D5/0094

Abstract: An apparatus for dicing a semiconductor wafer having a circuit side, an underside, and a street index that defines dice on the semiconductor wafer is disclosed. The apparatus includes a support having a surface for supporting the underside of the semiconductor wafer and at least one recess in the surface corresponding to the street index of the semiconductor wafer.

Abstract translation: 公开了一种用于在半导体晶片上切割具有限定骰子的电路侧，下侧和街道指数的半导体晶片的设备。 该装置包括支撑体，其具有用于支撑半导体晶片的下侧的表面和与半导体晶片的街道索引相对应的表面中的至少一个凹部。

公开(公告)号：US06210984B1

公开(公告)日：2001-04-03

申请号：US09399640

申请日：1999-09-20

Applicant: Warren M. Farnworth ,  Alan G. Wood ,  John O. Jacobson ,  David R. Hembree ,  James M. Wark ,  Jennifer L. Folaron ,  Robert J. Folaron ,  Jay C. Nelson ,  Lelan D. Warren

Inventor： Warren M. Farnworth ,  Alan G. Wood ,  John O. Jacobson ,  David R. Hembree ,  James M. Wark ,  Jennifer L. Folaron ,  Robert J. Folaron ,  Jay C. Nelson ,  Lelan D. Warren

IPC: H01L2166

CPC classification number: H01L21/67276 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2893 ,  G01R31/311 ,  H01L21/67126 ,  H01L21/67242 ,  H01L21/67259 ,  H01L21/681 ,  H01L24/74 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K13/08 ,  Y10T29/49004 ,  Y10T29/49131 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).

Abstract translation: 从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。 采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。 本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

公开(公告)号：US6140827A

公开(公告)日：2000-10-31

申请号：US994004

申请日：1997-12-18

Applicant: James M. Wark

Inventor： James M. Wark

IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28 ,  H05K3/32 ,  H05K3/40 ,  G01R31/02

CPC classification number: G01R1/07307 ,  G01R1/0483 ,  G01R31/2831 ,  G01R31/2886 ,  H05K3/325 ,  H05K3/4007

Abstract: A method and apparatus for testing unpackaged semiconductor dice having raised contact locations is disclosed. The apparatus uses a temporary interconnect wafer that is adapted to establish an electrical connection with the raised ball contact locations on the die without damage to the contact location. The interconnect is fabricated on a substrate, such as silicon, where contact members are formed in a pattern that matches the size and spacing of the contact locations on the die to be tested. The contact members on the interconnect wafer are formed as either pits, troughs, or spike contacts. The spike contacts penetrate through the oxide layer formed on the raised ball contact locations contact pad. Conductive traces are provided in both rows and columns and are terminated on the inner edges of the walls of the pits formed in the substrate. This arrangement allows a system to measure the continuity across the bump pad or ball contact locations of the integrated circuit die in order to establish that each solder ball location is properly attached. This allows the system to test for the presence and quality of the bumps or balls on the particular die being tested.

Abstract translation: 公开了一种用于测试具有凸起接触位置的未包装半导体晶片的方法和装置。 该装置使用临时互连晶片，其适于与模具上的凸起的球接触位置建立电连接，而不损坏接触位置。 互连制造在诸如硅的衬底上，其中接触构件以与待测试的管芯上的接触位置的尺寸和间距匹配的图案形成。 互连晶片上的接触构件形成为凹坑，凹槽或尖峰触点。 尖钉触头穿过形成在凸起的球接触位置接触垫上的氧化物层。 导电迹线设置在行和列中，并且终止于形成在基板中的凹坑的壁的内边缘。 这种布置允许系统测量集成电路管芯的凸块焊盘或球接触位置之间的连续性，以便确定每个焊球位置被适当地附接。 这允许系统测试在被测试的特定模具上的凸块或球的存在和质量。

公开(公告)号：US5952840A

公开(公告)日：1999-09-14

申请号：US770942

申请日：1996-12-31

Applicant: Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson

Inventor： Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson

IPC: G01R1/04 ,  G01R31/28 ,  G01R31/02

CPC classification number: G01R1/0491 ,  G01R31/2886

Abstract: A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.