公开(公告)号：US20090166868A1

公开(公告)日：2009-07-02

申请号：US12011750

申请日：2008-01-29

Applicant: Jong-Myeong Lee ,  Gil-Heyun Choi ,  Jong-Won Hong ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

Inventor： Jong-Myeong Lee ,  Gil-Heyun Choi ,  Jong-Won Hong ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/7684 ,  H01L21/76867 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first interlayer dielectric including a trench on a semiconductor layer, a mask pattern on the first interlayer dielectric, a first conductive pattern in the trench, and a second interlayer dielectric on the mask pattern. The second interlayer dielectric includes an opening over the first conductive pattern. A second conductive pattern is in the opening and is electrically connected to the first conductive pattern. The first conductive pattern has an upper surface lower than an upper surface of the mask pattern.

Abstract translation: 半导体器件包括在半导体层上包括沟槽的第一层间电介质，第一层间电介质上的掩模图案，沟槽中的第一导电图案和掩模图案上的第二层间电介质。 第二层间电介质包括在第一导电图案上的开口。 第二导电图案在开口中并且电连接到第一导电图案。 第一导电图案具有比掩模图案的上表面低的上表面。

公开(公告)号：US07547632B2

公开(公告)日：2009-06-16

申请号：US11675158

申请日：2007-02-15

Applicant: Jung-Hun Seo ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hee-Sook Park

Inventor： Jung-Hun Seo ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hee-Sook Park

IPC: H01L21/44

CPC classification number: C23C16/4408 ,  C23C16/54 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76861

Abstract: A metal deposition processing apparatus includes a first processing chamber configured for holding a semiconductor substrate therein. A second processing chamber is configured for holding the semiconductor substrate therein and for forming an upper metal layer thereon. A transfer chamber is connected to the first processing chamber and the second processing chamber. The transfer chamber is configured to transfer the semiconductor substrate between the first processing chamber and the second processing chamber.

Abstract translation: 金属沉积处理装置包括：第一处理室，被构造成用于将半导体基板保持在其中。 第二处理室构造成用于将半导体衬底保持在其中并用于在其上形成上金属层。 传送室连接到第一处理室和第二处理室。 传送室配置成在第一处理室和第二处理室之间传送半导体衬底。

公开(公告)号：US20090011583A1

公开(公告)日：2009-01-08

申请号：US12165805

申请日：2008-07-01

Applicant: Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

Inventor： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

IPC: H01L21/28

CPC classification number: H01L21/28176 ,  H01L21/76826 ,  H01L27/10855 ,  H01L27/11521

Abstract: A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.

Abstract translation: 在基板上形成栅极结构。 形成覆盖栅极结构的绝缘中间层。 在将绝缘中间层的表面暴露于氢气气氛的同时对基板进行热处理。 在热处理之后，在层间绝缘层上直接形成氮化硅层，在绝缘中间层上形成金属配线。 金属布线可以包括铜。 在将层间绝缘层的表面暴露于氢气气氛的同时对基板进行热处理之前，可以通过与基板接触的第一绝缘中间层形成插塞，并且金属布线可以电连接到插头。 插头可以包括钨。

公开(公告)号：US07452811B2

公开(公告)日：2008-11-18

申请号：US11425970

申请日：2006-06-22

Applicant: Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

Inventor： Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

IPC: H01L21/443

CPC classification number: H01L21/28556 ,  C23C16/34 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76862 ,  H01L21/76867 ,  H01L21/76877

Abstract: In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR1)(NR2R3)3 in which R1, R2 and R3 represent H or C1-C6 alkyl group are introduced onto the insulating interlayer. A portion of the tantalum amine derivatives is chemisorbed on the insulating interlayer. The rest of tantalum amine derivatives non-chemisorbed on the insulating interlayer is removed from the insulating interlayer. A reacting gas is introduced onto the insulating interlayer. A ligand in the tantalum amine derivatives chemisorbed on the insulating interlayer is removed from the tantalum amine derivatives by a chemical reaction between the reacting gas and the ligand to form a solid material including tantalum nitride. The solid material is accumulated on the insulating interlayer through repeating the above processes to form a wiring.

Abstract translation: 在使用原子层沉积形成半导体器件的布线的方法中，在基板上形成绝缘中间层。 由化学式Ta（NR 1）3（NR 2 R 3）3表示的钽胺衍生物，其中 R 1，R 2和R 3代表H或C 1 -C 6 >烷基引入到绝缘中间层上。 一部分钽胺衍生物被化学吸附在绝缘中间层上。 在绝缘中间层上除去非化学吸附在绝缘中间层上的其余的钽胺衍生物。 将反应气体引入到绝缘中间层上。 化学吸附在绝缘中间层上的钽胺衍生物中的配体通过反应气体和配位体之间的化学反应从钽胺衍生物中除去以形成包括氮化钽的固体材料。 通过重复上述处理，将固体材料积聚在绝缘层间，形成布线。

公开(公告)号：US20080012134A1

公开(公告)日：2008-01-17

申请号：US11770631

申请日：2007-06-28

Applicant: Kyung-In CHOI ,  Sang-Woo LEE ,  Jong-Myeong LEE ,  Jong-Won HONG ,  Hyun-Bae LEE

Inventor： Kyung-In CHOI ,  Sang-Woo LEE ,  Jong-Myeong LEE ,  Jong-Won HONG ,  Hyun-Bae LEE

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/5226 ,  H01L21/76846 ,  H01L21/76858 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metal interconnection structure is provided. The method includes forming an insulating layer on a semiconductor substrate including a first metal interconnection. The insulating layer is patterned to form an opening that exposes the first metal interconnection. A first diffusion barrier layer is formed on the exposed first metal interconnection. The first diffusion barrier layer comprises at least one of aluminum(Al), zirconium(Zr), silicon(Si), molybdenum(Mo), cobalt(Co), tungsten(W), ruthenium(Ru) and nickel(Ni). A second metal interconnection is formed on the first diffusion barrier layer. Metal atoms from the first metal interconnection are prevented from diffusing into the second metal interconnection by the first diffusion barrier layer. A metal interconnection structure having the first diffusion barrier layer is also provided.

Abstract translation: 提供一种形成金属互连结构的方法。 该方法包括在包括第一金属互连的半导体衬底上形成绝缘层。 图案化绝缘层以形成露出第一金属互连的开口。 在暴露的第一金属互连上形成第一扩散阻挡层。 第一扩散阻挡层包括铝（Al），锆（Zr），硅（Si），钼（Mo），钴（Co），钨（W），钌（Ru）和镍（Ni）中的至少一种。 在第一扩散阻挡层上形成第二金属互连。 通过第一扩散阻挡层防止来自第一金属互连的金属原子扩散到第二金属互连中。 还提供了具有第一扩散阻挡层的金属互连结构。

公开(公告)号：US06964922B2

公开(公告)日：2005-11-15

申请号：US10353386

申请日：2003-01-28

Applicant: Jong-myeong Lee ,  Hyeon-deok Lee ,  In-sun Park ,  Ju-bum Lee

Inventor： Jong-myeong Lee ,  Hyeon-deok Lee ,  In-sun Park ,  Ju-bum Lee

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/28562 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

Abstract: Methods of forming an integrated circuit device can include forming an interlevel dielectric film on an integrated circuit substrate including a conductive portion thereof. The interlevel dielectric film includes a contact hole therein exposing a portion of the conductive portion of the integrated circuit substrate, and the dielectric film includes a trench therein communicating with the contact hole wherein the trench is in a surface of the interlevel dielectric film opposite the integrated circuit substrate. A first metal layer is formed in the contact hole preferentially with respect to formation of the first metal layer on a surface of the interlevel dielectric film opposite the integrated circuit substrate. After preferentially forming the first metal layer in the contact hole, a second metal layer is formed on the surface of the interlevel dielectric film opposite the integrated circuit substrate.

Abstract translation: 形成集成电路器件的方法可以包括在包括其导电部分的集成电路衬底上形成层间电介质膜。 所述层间电介质膜包括露出所述集成电路基板的所述导电部分的一部分的接触孔，并且所述电介质膜包括与所述接触孔连通的沟槽，其中所述沟槽位于所述层间绝缘膜的与所述集成电路基板相对的表面中 电路基板。 相对于与集成电路基板相对的层间电介质膜的表面，优选在接触孔中形成第一金属层以形成第一金属层。 在接触孔中优先形成第一金属层之后，在与集成电路基板相对的层间绝缘膜的表面上形成第二金属层。

公开(公告)号：US20050179141A1

公开(公告)日：2005-08-18

申请号：US11095006

申请日：2005-03-31

Applicant: Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

Inventor： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L23/52

CPC classification number: H01L21/76843 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

公开(公告)号：US20050158990A1

公开(公告)日：2005-07-21

申请号：US11033781

申请日：2005-01-12

Applicant: Jae-hwa Park ,  Gil-heyun Choi ,  Jong-myeong Lee ,  Hee-sook Park

Inventor： Jae-hwa Park ,  Gil-heyun Choi ,  Jong-myeong Lee ,  Hee-sook Park

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L29/15

CPC classification number: H01L21/7684 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76856

Abstract: A method of forming a conductive plug for an integrated circuit device may include forming an insulating layer on an integrated circuit substrate with the insulating layer having a surface opposite the substrate and a recess therein. A titanium (Ti) layer may be formed on sidewalls of the recess and on the surface of the insulating layer opposite the substrate. After forming the titanium (Ti) layer, a reaction reducing layer may be formed on portions of the titanium layer on the surface of the insulating layer opposite the substrate by at least one of ionized physical vapour deposition (iPVD) and/or nitriding a portion of the titanium layer, and the reaction reducing layer may include a material other than titanium. After forming the reaction reducing layer, a TiN layer may be formed on the reaction reducing layer and on sidewalls of the recess in the insulating layer using metal organic chemical vapour deposition (MOCVD). After forming the TiN layer, a conductive plug may be formed on the TiN layer in the recess in the insulating layer.

Abstract translation: 形成用于集成电路器件的导电插塞的方法可以包括在集成电路衬底上形成绝缘层，绝缘层具有与衬底相对的表面和凹部。 钛（Ti）层可以形成在凹槽的侧壁上，并且在绝缘层的与衬底相对的表面上。 在形成钛（Ti）层之后，可以通过离子物理气相沉积（iPVD）和/或氮化一部分中的至少一种，在绝缘层的与基板相对的表面上的钛层的部分上形成反应还原层 的钛层，反应还原层可以包括钛以外的材料。 在形成反应还原层之后，可以使用金属有机化学气相沉积（MOCVD）在反应还原层上和在绝缘层的凹槽的侧壁上形成TiN层。 在形成TiN层之后，可以在绝缘层的凹部中的TiN层上形成导电塞。

公开(公告)号：US20050020042A1

公开(公告)日：2005-01-27

申请号：US10780244

申请日：2004-02-17

Applicant: Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

Inventor： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/28061 ,  H01L21/28088 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

Abstract translation: 形成具有金属栅电极的半导体器件的方法包括在半导体衬底上顺序地形成栅极绝缘体，栅极多晶硅层和金属栅极层。 金属栅极层和栅极多晶硅层被顺序地图案化以形成包括堆叠栅极多晶硅图案和金属栅极图案的栅极图案。 形成氧化阻挡层以覆盖金属 - 栅极图案的侧壁的至少一部分。

公开(公告)号：US06673718B1

公开(公告)日：2004-01-06

申请号：US10305244

申请日：2002-11-27

Applicant: Jong-Myeong Lee ,  In-Sun Park ,  Hyeon-Deok Lee ,  Jong-Sik Chun

Inventor： Jong-Myeong Lee ,  In-Sun Park ,  Hyeon-Deok Lee ,  Jong-Sik Chun

IPC: H01L2144

CPC classification number: H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

Abstract: An aluminum wiring is selectively formed within a contact hole or groove of a substrate. An intermediate layer which includes nitrogen is formed over the main surface of a substrate and over the interior surface of the contact hole or groove. A first surface portion of the intermediate layer which is located over the main surface of the substrate is treated with a plasma to form a passivity layer at the first surface portion of the intermediate layer. Then, without an intervening vacuum break, an aluminum film is CAD deposited only over a second surface portion of the intermediate layer which is located over the interior surface of the contact hole or recess. The plasma treatment of the first surface portion of the intermediate layer prevents the CAD deposition of the aluminum film over the first surface portion of the intermediate layer.

Abstract translation: 在基板的接触孔或凹槽内选择性地形成铝布线。 包含氮的中间层形成在基板的主表面上并在接触孔或凹槽的内表面上方。 用等离子体处理位于基板的主表面上方的中间层的第一表面部分，以在中间层的第一表面部分处形成被动层。 然后，没有中间真空断裂，铝膜仅沉积在中间层的位于接触孔或凹槽的内表面上方的第二表面部分上。 中间层的第一表面部分的等离子体处理防止铝膜在中间层的第一表面部分上的CAD沉积。