公开(公告)号：US20070015355A1

公开(公告)日：2007-01-18

申请号：US11179265

申请日：2005-07-12

Applicant: Keng-Chu Lin ,  Chung-Chi Ko ,  Yi-Chi Liao

Inventor： Keng-Chu Lin ,  Chung-Chi Ko ,  Yi-Chi Liao

IPC: H01L21/469

CPC classification number: H01L21/76834 ,  H01L21/76825

Abstract: A method for forming an interconnect structure. A substrate is provided with a low-k dielectric layer thereon. At least one conductive feature is then formed in the low-k dielectric layer. A cap layer is formed overlying the low-k dielectric layer, and the conductive feature and the low-k dielectric layer is then subjected to an energy source to reduce a dielectric constant thereof.

Abstract translation: 一种形成互连结构的方法。 衬底上设置有低k电介质层。 然后在低k电介质层中形成至少一个导电特征。 形成覆盖低k电介质层的覆盖层，然后使导电特征和低k电介质层经受能量源以降低其介电常数。

公开(公告)号：US20060172531A1

公开(公告)日：2006-08-03

申请号：US11048518

申请日：2005-02-01

Applicant: Keng-Chu Lin ,  Shwang-Ming Cheng ,  Ming Yeh ,  Tien-I Bao

Inventor： Keng-Chu Lin ,  Shwang-Ming Cheng ,  Ming Yeh ,  Tien-I Bao

IPC: H01L21/4763

CPC classification number: H01L21/76831

Abstract: A semiconductor method of manufacturing involving porous and/or carbon containing, low-k dielectrics is provided. The method includes forming a hydrocarbon of the general composition CxHy on the surface of the low-k dielectric. The hydrocarbon layer includes depositing a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing carbon depletion damage caused by plasma processing or etching. Surface dielectric pores damaged by plasma processing are also repaired by sealing them with the CXHY layer. Embodiments include semiconductor devices, such as devices having damascene interconnect structures, manufacturing using methods provided.

Abstract translation: 提供了涉及含有多孔和/或碳的低k电介质的半导体制造方法。 该方法包括在低k电介质的表面上形成总体组成为C H 的烃。 烃层包括沉积前体材料，优选C 2 H 4 H 3或（CH 3 CH 3）2 CH 3， 6> 6 6 3。 根据本发明的实施例，碳扩散到低k电介质中，从而减少由等离子体处理或蚀刻引起的碳损耗损伤。 通过等离子体处理损坏的表面电介质孔也通过用C H 层密封来修复。 实施例包括半导体器件，例如具有镶嵌互连结构的器件，使用提供的方法的制造。

公开(公告)号：US20050269957A1

公开(公告)日：2005-12-08

申请号：US11056303

申请日：2005-02-11

Applicant: Hong-Ru Guo ,  Keng-Chu Lin ,  Chen-Chung Yang ,  Chia-Tin Chung

Inventor： Hong-Ru Guo ,  Keng-Chu Lin ,  Chen-Chung Yang ,  Chia-Tin Chung

IPC: G09G3/10

CPC classification number: G09G3/3233 ,  G09G3/3291 ,  G09G2320/0233

Abstract: A driving circuit of a pixel of an active organic electro-luminescence device for driving an emitting device in the pixel of the active organic electro-luminescence device is provided. A voltage sensor is adapted for sensing the voltage of the emitting device and sending out the signal according to the voltage. A compensation unit is adapted for receiving the signal output from the voltage sensor. A compensating signal is sent to an emitting device driving unit for compensating the data signal input into the pixel of active organic electro-luminescence device so as to improve uniformity in the brightness of the active organic electro-luminescence device.

Abstract translation: 提供了用于驱动有源有机电致发光器件的像素中的发光器件的有源有机电致发光器件的像素的驱动电路。 电压传感器适于感测发射装置的电压并根据电压发出信号。 补偿单元适于接收从电压传感器输出的信号。 补偿信号被发送到发射器件驱动单元，用于补偿输入到有源有机电致发光器件的像素中的数据信号，以便改善有源有机电致发光器件的亮度的均匀性。

公开(公告)号：US06638853B1

公开(公告)日：2003-10-28

申请号：US10190148

申请日：2002-07-03

Applicant: Hung-Wen Sue ,  Chung-Shi Liu ,  Wen-Chin Chiou ,  Keng-Chu Lin

Inventor： Hung-Wen Sue ,  Chung-Shi Liu ,  Wen-Chin Chiou ,  Keng-Chu Lin

IPC: H01L214763

CPC classification number: H01L21/76808

Abstract: A method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process including providing a semiconductor wafer having a process surface including a first anisotropically etched opening extending through a semiconductor wafer thickness portion including an underlying dielectric insulating layer; blanket depositing a polymeric resinous layer over the semiconductor wafer process surface to include filling the first anisotropically etched opening; curing the polymeric resinous layer by exposing the polymeric resinous layer to at least one of thermal or photonic energy to initiate polymer cross linking; chemically mechanically polishing (CMP) the polymeric resinous layer to substantially remove the polymeric resinous layer thickness above the process surface; and, forming a photolithographically patterned photoresist layer over the process surface for forming a second anisotropically etched opening overlying and encompassing the first anisotropically etched opening.

Abstract translation: 一种用于改善光刻图案化工艺以避免半导体制造工艺中未发展的光致抗蚀剂污染的方法，包括提供具有工艺表面的半导体晶片，所述工艺表面包括延伸穿过包括下面的介电绝缘层的半导体晶片厚度部分的第一各向异性蚀刻的开口; 在所述半导体晶片工艺表面上覆盖沉积聚合物树脂层以包括填充所述第一各向异性蚀刻的开口; 通过将聚合物树脂层暴露于热能或光子能中的至少一种以引发聚合物交联来固化聚合物树脂层; 化学机械抛光（CMP）聚合物树脂层以基本上去除工艺表面上方的聚合树脂层厚度; 以及在所述工艺表面上形成光刻图案化的光致抗蚀剂层，以形成覆盖并包围所述第一各向异性蚀刻的开口的第二各向异性蚀刻的开口。

公开(公告)号：US6136688A

公开(公告)日：2000-10-24

申请号：US421508

申请日：1999-10-20

Applicant: Keng-Chu Lin ,  Kuang-Chao Chen ,  Rong-Wu Chien ,  Lian-Fa Hung ,  Pang-Yen Tsai ,  Ching-Chang Chang

Inventor： Keng-Chu Lin ,  Kuang-Chao Chen ,  Rong-Wu Chien ,  Lian-Fa Hung ,  Pang-Yen Tsai ,  Ching-Chang Chang

IPC: H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/02126 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31625 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/3185

Abstract: The present invention is a method of capping with a high compressive stress oxide, a boron phospho-silicate glass (BPSG) interlayer dielectric (ILD) gapfill that has been deposited on a topographic silicon substrate, in order to eliminate the formation of cracks in subsequently deposited silicon nitride (SiN) layers, other subsequently deposited high tensile stress layers and cracks that result from other post-BPSG deposition high temperature processes.

Abstract translation: 本发明是一种用高压缩应力氧化物覆盖的方法，已经沉积在地形硅衬底上的硼磷硅酸盐玻璃（BPSG）层间电介质（ILD）间隙填料，以便于随后消除裂纹的形成 沉积的氮化硅（SiN）层，其它随后沉积的高拉伸应力层和由其他后BPSG沉积高温工艺引起的裂纹。

公开(公告)号：US09349689B2

公开(公告)日：2016-05-24

申请号：US13452446

申请日：2012-04-20

Applicant: Hui-Chun Yang ,  Mei-Ling Chen ,  Keng-Chu Lin ,  Joung-Wei Liou

Inventor： Hui-Chun Yang ,  Mei-Ling Chen ,  Keng-Chu Lin ,  Joung-Wei Liou

IPC: H01L21/4763 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/28562 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.

Abstract translation: 公开了半导体器件，其制造方法以及形成其导电特征的方法。 半导体器件包括设置在工件上方的绝缘材料层。 绝缘材料层包括含有约13％或更多碳（C）的含硅材料。 导电特征设置在绝缘材料层内。 导电特征包括设置在其顶表面上的覆盖层。

公开(公告)号：US09130017B2

公开(公告)日：2015-09-08

申请号：US13220245

申请日：2011-08-29

Applicant: Po-Cheng Shih ,  Chung-Chi Ko ,  Keng-Chu Lin

Inventor： Po-Cheng Shih ,  Chung-Chi Ko ,  Keng-Chu Lin

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76811 ,  H01L21/02167 ,  H01L21/02271 ,  H01L21/31144 ,  H01L21/76813

Abstract: A method includes forming a hard mask over a low-k dielectric layer, and patterning the hard mask to form an opening. A stress tuning layer is formed over the low-k dielectric layer and in physical contact with the hard mask. The stress tuning layer has an inherent stress, wherein the inherent stress is a near-zero stress or a tensile stress. The low-k dielectric layer is etched to form a trench aligned to the opening, wherein the step of etching is performed using the hard mask as an etching mask.

Abstract translation: 一种方法包括在低k电介质层上形成硬掩模，并对硬掩模进行图案化以形成开口。 应力调整层形成在低k电介质层上并与硬掩模物理接触。 应力调整层具有固有应力，其中固有应力为近零应力或拉伸应力。 蚀刻低k电介质层以形成与开口对准的沟槽，其中使用硬掩模作为蚀刻掩模进行蚀刻步骤。

公开(公告)号：US09087877B2

公开(公告)日：2015-07-21

申请号：US11585610

申请日：2006-10-24

Applicant: Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

Inventor： Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/76826

Abstract: A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.

Abstract translation: 一种用于形成集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，形成至少覆盖开口侧壁的介电阻挡层，进行处理以改善 介电阻挡层的润湿能力，并用导电材料填充开口，其中导电材料与电介质阻挡层接触。

公开(公告)号：US09054110B2

公开(公告)日：2015-06-09

申请号：US13204507

申请日：2011-08-05

Applicant: Joung-Wei Liou ,  Hui-Chun Yang ,  Yu-Yun Peng ,  Keng-Chu Lin

Inventor： Joung-Wei Liou ,  Hui-Chun Yang ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L21/4763 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76879 ,  H01L21/02123 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/31 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.

Abstract translation: 提供了一种用于低k电介质层的系统和方法。 优选的实施方案包括形成基质并在基质内形成致孔剂。 致孔剂包括具有少于15个碳原子和大量单键的有机环结构。 此外，致孔剂可能具有大于1.3的粘度和小于0.5的雷诺数。

公开(公告)号：US08993435B2

公开(公告)日：2015-03-31

申请号：US12724229

申请日：2010-03-15

Applicant: Kuan-Chen Wang ,  Po-Cheng Shih ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

Inventor： Kuan-Chen Wang ,  Po-Cheng Shih ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L21/4763 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.

Abstract translation: 在互连结构的形成中，在电介质层中形成金属特征。 使用前体和包含碳作为前体的碳源气体在金属特征和电介质层上形成蚀刻停止层（ESL）。 碳源气体不含二氧化碳（CO2）。 前体选自基本上由1-甲基硅烷（1MS），2-甲基硅烷（2MS），3-甲基硅烷（3MS），4-甲基硅烷（4MS）及其组合组成的组。