公开(公告)号：US09041205B2

公开(公告)日：2015-05-26

申请号：US13930086

申请日：2013-06-28

Applicant: Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

Inventor： Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/04 ,  H01L23/538 ,  H01L23/522 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/37002 ,  H01L2924/00 ,  H01L2924/01033

Abstract: A semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

Abstract translation: 一种半导体器件包括其上具有集成电路的表面的半导体管芯，其通过多个导电触点耦合到半导体封装衬底的最上层金属化层的接触焊盘。 多个离散金属平面设置在半导体封装基板的最上层的金属化层上，每个金属平面从平面图的角度位于半导体管芯的周边的角部。 从半导体封装基板的最上层的金属化层设置微带布线，从平面图的角度来看，位于半导体管芯的外围。

公开(公告)号：US10468352B2

公开(公告)日：2019-11-05

申请号：US15503658

申请日：2014-09-19

Applicant: Kyu-Oh Lee

Inventor： Kyu-Oh Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L25/065 ,  H05K3/46

Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US09391025B2

公开(公告)日：2016-07-12

申请号：US14692400

申请日：2015-04-21

Applicant: Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

Inventor： Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/522 ,  H01L23/13 ,  H01L21/56 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/37002 ,  H01L2924/00 ,  H01L2924/01033

Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

Abstract translation: 描述了用于电子部件的可靠的微带布线布置。 在一个示例中，半导体器件包括具有其上具有集成电路的表面的半导体管芯，其通过多个导电触点耦合到半导体封装衬底的最上层金属化层的接触焊盘。 多个离散金属平面设置在半导体封装基板的最上层的金属化层上，每个金属平面从平面图的角度位于半导体管芯的周边的角部。 从半导体封装基板的最上层的金属化层设置微带布线，从平面图的角度来看，位于半导体管芯的外围。

公开(公告)号：US20120161330A1

公开(公告)日：2012-06-28

申请号：US12975934

申请日：2010-12-22

Applicant: Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

Inventor： Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC: H01L23/48 ,  H01L21/50 ,  H01L21/52

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract translation: 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。

公开(公告)号：US10157847B2

公开(公告)日：2018-12-18

申请号：US15503658

申请日：2014-09-19

Applicant: Kyu-Oh Lee

Inventor： Kyu-Oh Lee

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H05K3/46 ,  H01L25/065

Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20170271264A1

公开(公告)日：2017-09-21

申请号：US15503658

申请日：2014-09-19

Applicant: Kyu-Oh LEE

Inventor： Kyu-Oh LEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L21/48

Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US08835217B2

公开(公告)日：2014-09-16

申请号：US12975934

申请日：2010-12-22

Applicant: Mark S Hlad ,  Islam A Salama ,  Mihir K Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

Inventor： Mark S Hlad ,  Islam A Salama ,  Mihir K Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC: H01L21/44 ,  H01L23/02

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract translation: 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。