Abstract:
In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.
Abstract:
In a logically partitioned computer system, a partition manager maintains and controls master encryption keys for the different partitions. Preferably, processes executing within a partition have no direct access to real memory, addresses in the partition's memory space being mapped to real memory by the partition manager. The partition manager maintains master keys at real memory addresses inaccessible to processes executing in the partitions. Preferably, a special hardware register stores a pointer to the current key, and is read only by a hardware crypto-engine to encrypt/decrypt data. The crypto-engine returns the encrypted/decrypted data, but does not output the key itself or its location.
Abstract:
A microcode branch, to one of a number of possible control words (sixteen control words are described), is based upon (1) the remaining operand length that is to be processed by a left to right instruction, and (2) by the byte alignment of the portion of the operand that currently resides in main storage interface registers. As a left to right instruction is being executed, the operand's new length and its new alignment, as they both will exist after a control word is executed, are determined. The new length and the new alignment are used to determine the addess of the next control word. A 16-way branch instruction has branch legs that are determined by the number of operand bytes that are left to be processed, and by the alignment of two operands in two storage registers that interface with main storage. This method and arrangement for microcode branching maximizes the amount of data that can be processed per processor cycle by the hardware upon execution of a left to right instruction.