公开(公告)号：US20060258159A1

公开(公告)日：2006-11-16

申请号：US11130078

申请日：2005-05-16

Applicant: Matthew Colburn ,  Ricardo Donaton ,  Conal Murray ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Theodorus Eduardus Fransiscus Standaert ,  Xiao Liu

Inventor： Matthew Colburn ,  Ricardo Donaton ,  Conal Murray ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Theodorus Eduardus Fransiscus Standaert ,  Xiao Liu

IPC: H01B13/00 ,  H01L21/302 ,  B44C1/22

CPC classification number: H01L21/32139 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/7682

Abstract: A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.

Abstract translation: 用于制备电子结构的方法包括用牺牲多层硬掩模堆叠涂覆衬底叠层，在涂覆在多层硬掩模堆叠的最上层上的抗蚀剂层中形成图案，将图案转移到硬掩模堆叠中，阻挡部分 图案，然后将图案的未封闭部分转印到基底叠层中。 使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。 要强调的是，该摘要被提供以符合要求抽象的规则，这将允许搜索者或其他读者快速地确定技术公开的主题。 提交它的理解是，它不会用于解释或限制所附权利要求的范围或含义。

公开(公告)号：US20060244146A1

公开(公告)日：2006-11-02

申请号：US11474420

申请日：2006-06-26

Applicant: Matthew Colburn

Inventor： Matthew Colburn

IPC: H01L23/52

CPC classification number: H01L21/76835 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76829

Abstract: Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.

Abstract translation: 互连双镶嵌结构通过沉积在至少一个介电层的层上制造，掩模形成层用于提供双镶嵌结构的通孔级掩模层; 在通孔级掩模层中形成细长的通孔图案; 沉积一层线路电介质并通过线路级电介质层产生线路图案，并且通过细长通孔电平图案和线路电平图案的投影交点传送线路图案，从而产生对准的双 大马士革结构。 导电衬里层沉积在双镶嵌结构中，然后用导电填充金属填充双镶嵌结构以形成一组金属线。 金属和衬里层被平坦化。

公开(公告)号：US20060228653A1

公开(公告)日：2006-10-12

申请号：US10907688

申请日：2005-04-12

Applicant: Matthew Colburn ,  Dmitriy Shneyder ,  Shahab Siddiqui

Inventor： Matthew Colburn ,  Dmitriy Shneyder ,  Shahab Siddiqui

IPC: G03C5/00

CPC classification number: G03F7/168 ,  G03F7/325 ,  Y10S438/922 ,  Y10S977/733 ,  Y10S977/734

Abstract: Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO2) as a carrier or chlorodiflouromethane itself in supercritical form. The invention also includes a method of forming a nano-structure including exposing a polymeric film to a polar supercritical solvent to develop at least a portion of the polymeric film. The invention also includes a method of removing a poly(methyl methacrylate-b-styrene) (PMMA-b-S) based resist using a polar supercritical solvent.

Abstract translation: 公开了使用极性超临界溶剂显影或除去嵌段共聚物膜的选择区域以溶解选择部分的方法。 在一个实施方案中，极性超临界溶剂包括氯二氟甲烷，其可以使用超临界二氧化碳（CO 2 CO 2）作为载体或氯二氟乙烷本身以超临界形式暴露于嵌段共聚物膜。 本发明还包括形成纳米结构的方法，包括将聚合物膜暴露于极性超临界溶剂以形成至少一部分聚合物膜。 本发明还包括使用极性超临界溶剂除去聚（甲基丙烯酸甲酯-b-苯乙烯）（PMMA-b-S）基抗蚀剂的方法。

公开(公告)号：US20060157898A1

公开(公告)日：2006-07-20

申请号：US11037890

申请日：2005-01-18

Applicant: Matthew Colburn ,  Yves Martin ,  Charles Rettner ,  Theodore van Kessel ,  Hematha Wickramasinghe

Inventor： Matthew Colburn ,  Yves Martin ,  Charles Rettner ,  Theodore van Kessel ,  Hematha Wickramasinghe

IPC: B29C35/08

CPC classification number: G03F7/0002 ,  B01D2239/045 ,  B82Y10/00 ,  B82Y40/00 ,  G03F9/7011 ,  G03F9/7019

Abstract: A method (and resultant structure) of forming a plurality of masks, includes creating a reference template, using imprint lithography to print at least one reference template alignment mark on all of a plurality of mask blanks for a given chip set, and printing sub-patterns on each of the plurality of mask blanks, and aligning the sub-patterns to the at least one reference template alignment mark.

Abstract translation: 一种形成多个掩模的方法（和结果）包括使用压印光刻法创建参考模板以在给定芯片组的所有多个掩模坯料上打印至少一个参考模板对准标记， 所述多个掩模坯料中的每一个上的图案，以及将所述子图案对准所述至少一个参考模板对准标记。

公开(公告)号：US20060110890A1

公开(公告)日：2006-05-25

申请号：US10992072

申请日：2004-11-19

Applicant: Matthew Colburn ,  Yves Martin ,  Theodore van Kessel ,  Hematha K. Wickramasinghe

Inventor： Matthew Colburn ,  Yves Martin ,  Theodore van Kessel ,  Hematha K. Wickramasinghe

IPC: H01L21/76

CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

Abstract: A method (and apparatus) of replicating a pattern on a structure, includes using imprint lithography to replicate a pattern formed on a first structure onto a portion of a second structure.

Abstract translation: 在结构上复制图案的方法（和装置）包括使用压印光刻将形成在第一结构上的图案复制到第二结构的一部分上。

公开(公告)号：US20050233597A1

公开(公告)日：2005-10-20

申请号：US11143793

申请日：2005-06-02

Applicant: Matthew Colburn ,  Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian

Inventor： Matthew Colburn ,  Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian

IPC: H01L21/027 ,  B32B3/00 ,  G03F7/00 ,  G03F7/16 ,  G03F7/26 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/469

CPC classification number: H05K3/0079 ,  H01L21/0331 ,  H01L21/76849 ,  H05K3/282 ,  H05K2203/1173 ,  Y10T428/24802

Abstract: A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.

Abstract translation: 一种用于在衬底上的现有图案上形成自对准图案的方法，包括在载体中涂覆含有掩蔽材料的溶液的涂层，所述掩模材料对现有图案的部分具有亲和力; 并且允许掩模材料的至少一部分优先组装到现有图案的部分。 该图案可以由具有第一原子组成的衬底的第一组区域和第二组衬底的区域组成，其具有不同于第一组成的第二原子组成。 第一组区域可以包括一个或多个金属元件，并且第二组区域可以包括电介质。 可以将第一和第二区域处理成具有不同的表面性质。 按照该方法制造的结构。 用于练习该方法的组合物。

公开(公告)号：US06842229B2

公开(公告)日：2005-01-11

申请号：US10747795

申请日：2003-12-29

Applicant: Sidlgata V. Sreenivasan ,  Byung J. Choi ,  Matthew Colburn ,  Todd Bailey

Inventor： Sidlgata V. Sreenivasan ,  Byung J. Choi ,  Matthew Colburn ,  Todd Bailey

IPC: G02B5/18 ,  B29C35/08 ,  B29C37/00 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  G03B27/62 ,  G03B27/58

CPC classification number: B29C35/0888 ,  B29C37/0053 ,  B29C43/003 ,  B29C43/021 ,  B29C2035/0827 ,  B29C2043/025 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F9/00 ,  Y10S101/36 ,  Y10T428/24802

Abstract: A system of determining and correcting alignment during imprint lithography process is described. During an imprint lithographic process the template may be aligned with the substrate by the use of alignment marks disposed on both the template and substrate. The alignment may be determined and corrected for before the layer is processed.

Abstract translation: 描述了在压印光刻工艺期间确定和校正对准的系统。 在压印光刻工艺期间，模板可以通过使用设置在模板和衬底上的对准标记与衬底对准。 可以在层被处理之前确定和校正对准。

公开(公告)号：US20080038923A1

公开(公告)日：2008-02-14

申请号：US11851123

申请日：2007-09-06

Applicant: Daniel EDELSTEIN ,  Matthew COLBURN ,  Edward COONEY ,  Timothy DALTON ,  John FITZSIMMONS ,  Jeffrey GAMBINO ,  Elbert HUANG ,  Michael LANE ,  Vincent MCGAHAY ,  Lee NICHOLSON ,  Satyanarayana NITTA ,  Sampath PURUSHOTHAMAN ,  Sujatha SANKARAN ,  Thomas SHAW ,  Andrew SIMON ,  Anthony STAMPER

Inventor： Daniel EDELSTEIN ,  Matthew COLBURN ,  Edward COONEY ,  Timothy DALTON ,  John FITZSIMMONS ,  Jeffrey GAMBINO ,  Elbert HUANG ,  Michael LANE ,  Vincent MCGAHAY ,  Lee NICHOLSON ,  Satyanarayana NITTA ,  Sampath PURUSHOTHAMAN ,  Sujatha SANKARAN ,  Thomas SHAW ,  Andrew SIMON ,  Anthony STAMPER

IPC: H01L21/311

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

Abstract translation: 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越至少一个互连的侧壁。

公开(公告)号：US20070264588A1

公开(公告)日：2007-11-15

申请号：US10864214

申请日：2004-06-09

Applicant: Sidlgata Sreenivasan ,  Byung-Jin Choi ,  Matthew Colburn ,  Todd Bailey

Inventor： Sidlgata Sreenivasan ,  Byung-Jin Choi ,  Matthew Colburn ,  Todd Bailey

IPC: G03C5/00 ,  B29C35/08

CPC classification number: B29C35/0888 ,  B29C37/0053 ,  B29C43/003 ,  B29C43/021 ,  B29C2035/0827 ,  B29C2043/025 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F9/00 ,  Y10S101/36 ,  Y10T428/24802

Abstract: The present invention includes an imprint lithography system for impinging a flux of light upon a liquid to polymerize the liquid, the system including, a source of light producing the flux of light; and a template having overlay marks being disposed between the liquid and the source of light and being opaque to the flux of light, with a pitch of the overlay marks establishing a polarization of the flux of light such that the flux of light impinges upon and polymerizes the liquid in superimposition with the overlay marks.

Abstract translation: 本发明包括一种用于将光束照射在液体上以使液体聚合的压印光刻系统，该系统包括产生光通量的光源; 并且具有覆盖标记的模板设置在液体和光源之间，并且对于光通量不透明，叠加标记的间距建立光通量的偏振，使得光束流入并聚合 液体与叠加标记叠加。

公开(公告)号：US20060258147A1

公开(公告)日：2006-11-16

申请号：US11405287

申请日：2006-04-17

Applicant: Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Anna Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

Inventor： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Anna Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

IPC: H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.