公开(公告)号：US09059000B2

公开(公告)日：2015-06-16

申请号：US12106586

申请日：2008-04-21

Applicant: Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

Inventor： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  G03F7/11

CPC classification number: H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

公开(公告)号：US20080254643A1

公开(公告)日：2008-10-16

申请号：US12143917

申请日：2008-06-23

Applicant: Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

Inventor： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC: H01L21/768

CPC classification number: H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Abstract translation: 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US07402532B2

公开(公告)日：2008-07-22

申请号：US11499220

申请日：2006-08-04

Applicant: Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

Inventor： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC: H01L23/48

CPC classification number: H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Abstract translation: 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US20080038923A1

公开(公告)日：2008-02-14

申请号：US11851123

申请日：2007-09-06

Applicant: Daniel EDELSTEIN ,  Matthew COLBURN ,  Edward COONEY ,  Timothy DALTON ,  John FITZSIMMONS ,  Jeffrey GAMBINO ,  Elbert HUANG ,  Michael LANE ,  Vincent MCGAHAY ,  Lee NICHOLSON ,  Satyanarayana NITTA ,  Sampath PURUSHOTHAMAN ,  Sujatha SANKARAN ,  Thomas SHAW ,  Andrew SIMON ,  Anthony STAMPER

Inventor： Daniel EDELSTEIN ,  Matthew COLBURN ,  Edward COONEY ,  Timothy DALTON ,  John FITZSIMMONS ,  Jeffrey GAMBINO ,  Elbert HUANG ,  Michael LANE ,  Vincent MCGAHAY ,  Lee NICHOLSON ,  Satyanarayana NITTA ,  Sampath PURUSHOTHAMAN ,  Sujatha SANKARAN ,  Thomas SHAW ,  Andrew SIMON ,  Anthony STAMPER

IPC: H01L21/311

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

Abstract translation: 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越至少一个互连的侧壁。

公开(公告)号：US20070241398A1

公开(公告)日：2007-10-18

申请号：US11277306

申请日：2006-03-23

Applicant: Timothy Dalton ,  Marc Faucher ,  Paul Kartschoke ,  Peter Sandon

Inventor： Timothy Dalton ,  Marc Faucher ,  Paul Kartschoke ,  Peter Sandon

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L25/0657 ,  G01R31/318513 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.

Abstract translation: 半导体结构及其操作方法。 半导体结构包括第一半导体芯片和第二半导体芯片。 第一半导体芯片位于第二半导体芯片的顶部并结合到第二半导体芯片上。 第一和第二半导体芯片包括第一和第二电节点。 第二半导体芯片还包括第一比较电路。 半导体结构还包括通过将第一半导体芯片的第一电节点电连接到第二半导体芯片的第一比较电路的第一耦合。 第一比较电路能够（i）直接从第二电节点接收输入信号，（ii）通过第一耦合通路间接接收来自第一电节点的输入信号，以及（iii）将第一不匹配信号置于 对来自第一和第二电节点的输入信号的响应是不同的。

公开(公告)号：US20060258147A1

公开(公告)日：2006-11-16

申请号：US11405287

申请日：2006-04-17

Applicant: Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Anna Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

Inventor： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Anna Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

IPC: H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

公开(公告)号：US07052621B2

公开(公告)日：2006-05-30

申请号：US10461090

申请日：2003-06-13

Applicant: Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

Inventor： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

IPC: C23F1/00

CPC classification number: H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

Abstract translation: 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

公开(公告)号：US20060094230A1

公开(公告)日：2006-05-04

申请号：US10904323

申请日：2004-11-04

Applicant: Nicholas Fuller ,  Timothy Dalton ,  Raymond Joy ,  Yi-hsiung Lin ,  Chun Low

Inventor： Nicholas Fuller ,  Timothy Dalton ,  Raymond Joy ,  Yi-hsiung Lin ,  Chun Low

IPC: H01L21/4763

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/31138 ,  H01L21/31144

Abstract: Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.

Abstract translation: 公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。 该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层 层。 有机材料和无机材料之间的材料类型是交替的。 第三层被图案化为金属线和/或经由CD。 然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。 提供准确的CD形成和足够的抗蚀剂预算。

公开(公告)号：US20060081986A1

公开(公告)日：2006-04-20

申请号：US10964882

申请日：2004-10-14

Applicant: Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

Inventor： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC: H01L23/52

CPC classification number: H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

Abstract translation: 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

公开(公告)号：US20050266681A1

公开(公告)日：2005-12-01

申请号：US11182445

申请日：2005-07-15

Applicant: Timothy Dalton ,  Stephen Gates

Inventor： Timothy Dalton ,  Stephen Gates

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/02063 ,  H01L21/76814

Abstract: A method of fabricating BEOL interconnect structures on a semiconductor device having a plurality of via contacts with low via contact resistance is provided. The method includes the steps of: a) forming a porous or dense low k dielectric layer on a substrate; b) forming single or dual damascene etched openings in the low k dielectric; c) placing the substrate in a process chamber on a cold chuck at a temperature about −200° C. to about 25° C.; d) adding to the process chamber a condensable cleaning agent (CCA) to condense a layer of CCA within the etched openings on the substrate; and e) performing an activation step while the wafer remains cold at a temperature of about −200° C. to about 25° C. The via contacts are very stable during thermal cycles and during operation of the semiconductor device.

Abstract translation: 提供了在具有多个通孔接触电阻低的半导体器件上制造BEOL互连结构的方法。 该方法包括以下步骤：a）在衬底上形成多孔或致密的低k电介质层; b）在低k电介质中形成单个或双镶嵌蚀刻开口; c）将基板放置在约-200℃至约25℃的温度下的冷卡盘上的处理室中; d）向处理室中加入可冷凝清洁剂（CCA），以在衬底上的蚀刻开口内冷凝CCA层; 以及e）当晶片在约-200℃至约25℃的温度下保持冷时，执行激活步骤。在热循环期间和在半导体器件的操作期间，通孔触点是非常稳定的。