公开(公告)号：US07514801B2

公开(公告)日：2009-04-07

申请号：US10575581

申请日：2004-10-12

Applicant: Cornelis Gerardus Schriks ,  Paul Dijkstra ,  Peter Wilhelmus Maria Van De Water ,  Roelf Anco Jacob Groenhuis ,  Johannus Wilhelmus Weekamp

Inventor： Cornelis Gerardus Schriks ,  Paul Dijkstra ,  Peter Wilhelmus Maria Van De Water ,  Roelf Anco Jacob Groenhuis ,  Johannus Wilhelmus Weekamp

IPC: H01L23/28 ,  H01L23/52

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68377 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15313 ,  H01L2924/18301 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with a connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. The element is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

Abstract translation: 该装置具有载体和电气元件。 载体具有第一和相对侧，并且设置有连接层，中间层和接触垫。 元件存在于第一侧并且耦合到连接层。 该元件至少部分地被封装延伸到中间层中的图案之间的隔离区域中。 保护层存在于载体的第二侧，其覆盖接触垫和中间层之间的界面。

公开(公告)号：US20050153483A1

公开(公告)日：2005-07-14

申请号：US10510588

申请日：2003-04-10

Applicant: Roelf Groenhuis ,  Paul Dijkstra ,  Cornelis Schriks ,  Peter Van De Water

Inventor： Roelf Groenhuis ,  Paul Dijkstra ,  Cornelis Schriks ,  Peter Van De Water

IPC: H01L23/12 ,  A23G3/00 ,  A23G3/36 ,  A23G4/00 ,  A23G4/12 ,  A23L1/28 ,  A23L1/30 ,  A61K35/74 ,  A61K35/747 ,  A61P1/02 ,  C12N1/14 ,  C12R1/225 ,  H01L21/48 ,  H01L23/31 ,  H05K1/18 ,  H05K3/06 ,  H01L21/44 ,  H01L21/50

CPC classification number: H05K3/062 ,  A23G3/366 ,  A23G4/123 ,  A23L33/135 ,  A23Y2220/77 ,  A61K35/747 ,  C12R1/225 ,  H01L21/4828 ,  H01L21/4832 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/185 ,  H05K2201/0361 ,  H05K2203/0384 ,  H05K2203/1469 ,  H05K2203/1476 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The carrier (30) comprises a first etch mask (14), a first metal layer (11), an intermediate layer (12), a second metal layer (13) and a second etch mask (17). Both the first and the second etch mask (14, 17) can be provided in one step by means of electrochemical plating. After the first metal layer (11) and the intermediate layer (12) have been patterned through the first etch mask (14), an electric element (20) can be suitably attached to the carrier (30) using conductive means. In this patterning operations the intermediate layer (12) is etched further so as to create underetching below the first metal layer (11). After the provision of an encapsulation (40), the second metal layer (13) is patterned through the second etch mask (17). In this manner, a solderable device (10) is obtained without a photolithographic step during the assembly process.

Abstract translation: 载体（30）包括第一蚀刻掩模（14），第一金属层（11），中间层（12），第二金属层（13）和第二蚀刻掩模（17）。 可以通过电化学电镀在一个步骤中提供第一和第二蚀刻掩模（14,17）。 在通过第一蚀刻掩模（14）对第一金属层（11）和中间层（12）进行了图案化之后，可以使用导电装置将电气元件（20）适当地附接到载体（30）。 在这种图形化操作中，进一步蚀刻中间层（12），以便在第一金属层（11）下方产生不规则的凹凸。 在提供封装（40）之后，第二金属层（13）通过第二蚀刻掩模（17）构图。 以这种方式，在组装过程中获得无可光刻步骤的可焊接装置（10）。

公开(公告)号：US20120112351A1

公开(公告)日：2012-05-10

申请号：US13293016

申请日：2011-11-09

Applicant: Sven WALCZYK ,  Roelf Anco Jacob GROENHUIS ,  Paul Dijkstra ,  Emiel de BRUIN ,  Rolf Brenner

Inventor： Sven WALCZYK ,  Roelf Anco Jacob GROENHUIS ,  Paul Dijkstra ,  Emiel de BRUIN ,  Rolf Brenner

IPC: H01L23/48 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L23/3171 ,  H01L23/3178 ,  H01L2224/03464 ,  H01L2224/04026 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/94 ,  H01L2924/10155 ,  H01L2924/12036 ,  H01L2924/1304 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01046

Abstract: Disclosed is a method of manufacturing a discrete semiconductor device package (100), comprising providing a wafer comprising a plurality of semiconductor devices (50), each of said semiconductor devices comprising a substrate (110) having a top contact (130) and a bottom contact (150); partially sawing said wafer with a first sawing blade such that the semiconductor devices are partially separated from each other by respective incisions (20); lining said incisions with an electrically insulating film (160); and sawing through said incisions with a second sawing blade such that the semiconductor devices are fully separated from each other. A resulting discrete semiconductor device package (100) and a carrier (200) comprising such a discrete semiconductor device package (100) are also disclosed.

Abstract translation: 公开了一种制造分立半导体器件封装（100）的方法，包括提供包括多个半导体器件（50）的晶片，每个所述半导体器件包括具有顶部触点（130）和底部 接触（150）; 用第一锯刀部分地锯切所述晶片，使得半导体器件通过相应的切口（20）部分地彼此分离; 用电绝缘膜（160）衬里所述切口; 并且通过所述切口用第二锯切刀锯切，使得所述半导体器件彼此完全分离。 还公开了分立半导体器件封装（100）和包括这种分立半导体器件封装（100）的载体（200）。

公开(公告)号：US08153480B2

公开(公告)日：2012-04-10

申请号：US11996322

申请日：2006-07-24

Applicant: Geert Steenbruggen ,  Paul Dijkstra

Inventor： Geert Steenbruggen ,  Paul Dijkstra

IPC: H01L21/44 ,  H01L23/28

CPC classification number: H01L23/315 ,  H01L23/49558 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

Abstract: According to an example embodiment, there is method (100) for manufacturing a semiconductor device in an air-cavity package. For a device die having an active surface, a lead frame is provided (5), the lead frame has a top-side surface and an under-side surface, the lead frame has predetermined pad landings on the top-side surface. A laminate material is applied (10) to the top-side surface of the lead frame. In the laminate material, an air-cavity region and contact regions are defined (15, 20, 25, 30, 35). The contact regions provide electrical connections to the predetermined pad landings on the lead frame. With the active circuit surface in an orientation toward the laminate material, the device die is mounted (40, 45). The bond pads of the active surface circuit are connected with ball bonds to the predetermined pad landings on the lead frame. An air-cavity is formed between the active surface of the device die and the top-side surface of the lead frame.

Abstract translation: 根据示例性实施例，存在用于在空气腔封装中制造半导体器件的方法（100）。 对于具有活性表面的器件芯片，提供引线框架（5），引线框架具有顶侧表面和下侧表面，引线框架在顶侧表面上具有预定的焊盘平台。 将层压材料（10）施加到引线框架的顶侧表面。 在层压材料中，限定了空腔区域和接触区域（15,20,25,30,35）。 接触区域提供与引线框架上的预定焊盘平台的电连接。 在有源电路表面朝向层压材料的方向上，器件裸片被安装（40,45）。 有源表面电路的接合焊盘与引脚框架上的预定焊盘平台上的焊球连接。 在器件管芯的有源表面和引线框架的顶侧表面之间形成空腔。

公开(公告)号：US07944062B2

公开(公告)日：2011-05-17

申请号：US12092121

申请日：2006-10-27

Applicant: Roelf Anco Jacob Groenhuis ,  Paul Dijkstra

Inventor： Roelf Anco Jacob Groenhuis ,  Paul Dijkstra

IPC: H01L23/28

CPC classification number: H01L23/055 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/315 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00

Abstract: A die package (72) for a semiconductor die (20). A plurality of the die packages (72) are formed on a single carrier (10) by applying a body (55) of molding compound across a carrier (10) with an air cavity (70) defined in the molding compound about each of a plurality of device regions (12) of the carrier (10). After a semiconductor die (20) is attached inside the air cavity (70) of each device region (12) and electrically connected with at least one contact pad (14, 16, 18), a cover (68) is applied to close all of the air cavities (70). Following singulation, each semiconductor die (20) is located inside the sealed air cavity (70) of one die package (72). The molding compound of each die package (72) may be locked against movement relative to the device region (12) of the carrier (10) by locking features (30, 38, 48, 50). The locking features (30, 38, 48, 50) may constitute portions of contact pads (14, 16, 18) used to establish electrical communication paths from the semiconductor die (20) to the environment outside of the package (72).

Abstract translation: 一种用于半导体管芯（20）的管芯封装（72）。 多个模具封装（72）通过将模制化合物的主体（55）施加到载体（10）上而形成在单个载体（10）上，空腔（70）限定在模制化合物中， 载体（10）的多个装置区域（12）。 在半导体管芯（20）被安装在每个器件区域（12）的空气腔（70）内并且与至少一个接触焊盘（14,16,18）电连接之后，施加盖子（68）以关闭所有 的空气（70）。 在单片化之后，每个半导体管芯（20）位于一个管芯封装（72）的密封空气腔（70）的内部。 通过锁定特征（30,38,48,50），每个模具包装（72）的模制化合物可被锁定以防止相对于载体（10）的装置区域（12）移动。 锁定特征（30,38,48,50）可以构成用于建立从半导体管芯（20）到封装（72）外部的环境的电连通路径的接触焊盘（14,16,18）的部分。

公开(公告)号：US20090079050A1

公开(公告)日：2009-03-26

申请号：US11996322

申请日：2006-07-24

Applicant: Geert Steenbruggen ,  Paul Dijkstra

Inventor： Geert Steenbruggen ,  Paul Dijkstra

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/315 ,  H01L23/49558 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

Abstract: According to an example embodiment, there is method (100) for manufacturing a semiconductor device in an air-cavity package. For a device die having an active surface, a lead frame is provided (5), the lead frame has a top-side surface and an under-side surface, the lead frame has predetermined pad landings on the top-side surface. A laminate material is applied (10) to the top-side surface of the lead frame. In the laminate material, an air-cavity region and contact regions are defined (15, 20, 25, 30, 35). The contact regions provide electrical connections to the predetermined pad landings on the lead frame. With the active circuit surface in an orientation toward the laminate material, the device die is mounted (40, 45). The bond pads of the active surface circuit are connected with ball bonds to the predetermined pad landings on the lead frame. An air-cavity is formed between the active surface of the device die and the top-side surface of the lead frame.

Abstract translation: 根据示例性实施例，存在用于在空气腔封装中制造半导体器件的方法（100）。 对于具有活性表面的器件芯片，提供引线框架（5），引线框架具有顶侧表面和下侧表面，引线框架在顶侧表面上具有预定的焊盘平台。 将层压材料（10）施加到引线框架的顶侧表面。 在层压材料中，限定了空腔区域和接触区域（15,20,25,30,35）。 接触区域提供与引线框架上的预定焊盘平台的电连接。 在有源电路表面朝向层压材料的方向上，器件裸片被安装（40,45）。 有源表面电路的接合焊盘与引脚框架上的预定焊盘平台上的焊球连接。 在器件管芯的有源表面和引线框架的顶侧表面之间形成空腔。

公开(公告)号：US07247938B2

公开(公告)日：2007-07-24

申请号：US10510588

申请日：2003-04-10

Applicant: Roelf Anco Jacob Groenhuis ,  Paul Dijkstra ,  Cornelis Gerardus Schriks ,  Peter Wilhelmus Maria Van De Water

Inventor： Roelf Anco Jacob Groenhuis ,  Paul Dijkstra ,  Cornelis Gerardus Schriks ,  Peter Wilhelmus Maria Van De Water

IPC: H01L23/04

CPC classification number: H05K3/062 ,  A23G3/366 ,  A23G4/123 ,  A23L33/135 ,  A23Y2220/77 ,  A61K35/747 ,  C12R1/225 ,  H01L21/4828 ,  H01L21/4832 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/185 ,  H05K2201/0361 ,  H05K2203/0384 ,  H05K2203/1469 ,  H05K2203/1476 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The carrier (30) comprises a first etch mask (14), a first metal layer (11), an intermediate layer (12), a second metal layer (13) and a second etch mask (17). Both the first and the second etch mask (14, 17) can be provided in one step by means of electrochemical plating. After the first metal layer (11) and the intermediate layer (12) have been patterned through the first etch mask (14), an electric element (20) can be suitably attached to the carrier (30) using conductive means. In this patterning operation, the intermediate layer (12) is etched further so as to create underetching below the first metal layer (11). After the provision of an encapsulation (40), the second metal layer (13) is patterned through the second etch mask (17). In this manner, a solderable device (10) is obtained without a photolithographic step during the assembly process.

Abstract translation: 载体（30）包括第一蚀刻掩模（14），第一金属层（11），中间层（12），第二金属层（13）和第二蚀刻掩模（17）。 可以通过电化学电镀在一个步骤中提供第一和第二蚀刻掩模（14,17）。 在通过第一蚀刻掩模（14）对第一金属层（11）和中间层（12）进行了图案化之后，可以使用导电装置将电气元件（20）适当地附接到载体（30）。 在该图案化操作中，进一步蚀刻中间层（12），以便在第一金属层（11）的下面产生不规则的凹凸。 在提供封装（40）之后，第二金属层（13）通过第二蚀刻掩模（17）构图。 以这种方式，在组装过程中获得无可光刻步骤的可焊接装置（10）。

公开(公告)号：US08070971B2

公开(公告)日：2011-12-06

申请号：US11628517

申请日：2005-05-27

Applicant: Jan Kloosterman ,  Paul Dijkstra

Inventor： Jan Kloosterman ,  Paul Dijkstra

IPC: B44C1/22 ,  G03F1/00

CPC classification number: H01L23/3107 ,  H01L21/4832 ,  H01L23/49582 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  Y10T428/24479 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An improved method of etching a structure and a structure etched by the method is disclosed. The bottom side of a leadframe of an IC-package is an example of a structure, which advantageously may be etched with the disclosed method. The method includes the steps of providing an etch mask to the substrate to be etched. The etch mask comprising at least two sub-mask: a first sub-mask covering the area which substantially should remain after the etching process, and a second sub-mask covering an area to be removed in the etching process. The second sub-mask is a sacrificial mask in the form of a grid. The presence of the second sub-mask increases the etching speed in the area covered by it.

Abstract translation: 公开了通过该方法蚀刻结构和蚀刻结构的改进方法。 IC封装的引线框的底侧是结构的示例，其有利地可以利用所公开的方法进行蚀刻。 该方法包括以下步骤：向要蚀刻的衬底提供蚀刻掩模。 所述蚀刻掩模包括至少两个子掩模：覆盖在蚀刻工艺之后基本上应保留的区域的第一子掩模，以及覆盖在蚀刻工艺中待除去区域的第二子掩模。 第二子掩模是栅格形式的牺牲掩模。 第二子掩模的存在增加了其覆盖的区域中的蚀刻速度。

公开(公告)号：US07858444B2

公开(公告)日：2010-12-28

申请号：US12391064

申请日：2009-02-23

Applicant: Cornelis Gerardus Schriks ,  Paul Dijkstra ,  Peter Wilhelmus Maria Van De Water ,  Roelf Anco Jacob Groenhuis ,  Johannus Wilhelmus Weekamp

Inventor： Cornelis Gerardus Schriks ,  Paul Dijkstra ,  Peter Wilhelmus Maria Van De Water ,  Roelf Anco Jacob Groenhuis ,  Johannus Wilhelmus Weekamp

IPC: H01L23/02 ,  H01L23/28

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68377 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15313 ,  H01L2924/18301 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with an connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. It is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

Abstract translation: 该装置具有载体和电气元件。 载体具有第一和相对侧，并且设置有连接层，中间层和接触垫。 元件存在于第一侧并且耦合到连接层。 它至少部分地被封装延伸到中间层中的图案之间的隔离区域中。 保护层存在于载体的第二侧，其覆盖接触垫和中间层之间的界面。

公开(公告)号：US20100006996A1

公开(公告)日：2010-01-14

申请号：US12526619

申请日：2008-02-11

Applicant: Klaas Heres ,  Paul Dijkstra ,  Maarten Nollen

Inventor： Klaas Heres ,  Paul Dijkstra ,  Maarten Nollen

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/3121 ,  H01L21/4832 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/244 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A carrier (100) for bonding a semiconductor chip (114) onto is provided, wherein the carrier (100) comprises a die pad (101) and a plurality of contact pads (102), wherein each of the plurality of contact pads (102) comprises an electrically conductive multilayer stack, wherein the electrically conductive multilayer stack comprises a surface layer (109), a first buffer layer, and a first conductive layer (108). Furthermore, the first buffer layer comprises a material adapted to prevent diffusion of material of the surface layer (109) into the first conductive layer (108), and at least two of the contact pads (102) has an ultrafine pitch relative to each other.

Abstract translation: 提供一种用于将半导体芯片（114）接合到其上的载体（100），其中所述载体（100）包括芯片焊盘（101）和多个接触焊盘（102），其中所述多个接触焊盘 ）包括导电多层堆叠，其中所述导电多层堆叠包括表面层（109），第一缓冲层和第一导电层（108）。 此外，第一缓冲层包括适于防止表面层（109）的材料扩散到第一导电层（108）中的材料，并且至少两个接触焊盘（102）相对于彼此具有超细间距 。