公开(公告)号：US20160381796A1

公开(公告)日：2016-12-29

申请号：US15096993

申请日：2016-04-12

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Sung-Uk LEE ,  Il-Jong SEO ,  Jae-Hoon CHOI ,  Yong-Ho BAEK

IPC: H05K1/11 ,  H05K3/06

CPC classification number: H05K1/115 ,  H05K3/067 ,  H05K3/4647 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0361 ,  H05K2201/09854 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0384

Abstract: A printed circuit board and a method of manufacturing a printed circuit board are provided. The printed circuit board includes an insulating layer, a circuit layer embedded in the insulating layer, a solder resist layer disposed on one surface of the insulating layer, the solder resist layer having a cavity of a through-hole shape to expose a part of the circuit layer from the insulating layer, and a metal post embedded in the solder resist layer and exposed to outside via an opening of the solder resist layer, and the metal post includes a first post metal layer, a post barrier layer, and a second post metal layer disposed in that order.

Abstract translation: 提供印刷电路板和制造印刷电路板的方法。 印刷电路板包括绝缘层，嵌入绝缘层中的电路层，设置在绝缘层的一个表面上的阻焊层，阻焊层具有通孔形状的空腔，以暴露部分 电路层，以及嵌入到阻焊层中并经由阻焊层的开口暴露于外部的金属柱，金属柱包括第一后​​金属层，后阻挡层和第二柱 金属层。

公开(公告)号：US08028402B2

公开(公告)日：2011-10-04

申请号：US11775294

申请日：2007-07-10

Applicant: Hidehiro Nakamura ,  Akishi Nakaso ,  Shigeharu Arike ,  Fumio Inoue ,  Tetsuya Enomoto ,  Norio Moriike ,  Kousuke Hiroki

Inventor： Hidehiro Nakamura ,  Akishi Nakaso ,  Shigeharu Arike ,  Fumio Inoue ,  Tetsuya Enomoto ,  Norio Moriike ,  Kousuke Hiroki

IPC: H05K3/36 ,  H01R9/00 ,  H01K3/10

CPC classification number: H05K3/4617 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/244 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/4632 ,  H05K3/4647 ,  H05K2201/0141 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed is a manufacturing method of a multi-layer wiring board, which method includes: preparing connection boards, the connection boards having respectively an insulating resin composition layer, a connection conductor formed so as to pass through the insulating resin composition layer and a conductor circuit formed on the insulating resin composition layer and connected to the connection conductor; aligning the connection boards; and laminating the aligned connection boards by heating and pressing, so that the connection conductors, or the connection conductor and the conductor circuit, are conductively connected with each other, and the connection boards are mechanically connected with each other by the insulating resin composition layer. The connection boards are formed by specified processing, including use of a three-layer composite metallic layer.

Abstract translation: 公开了一种多层布线板的制造方法，该方法包括：准备连接板，连接板分别具有绝缘树脂组合物层，形成为穿过绝缘树脂组合物层的连接导体和导体电路 形成在绝缘树脂组合物层上并连接到连接导体; 对准连接板; 并且通过加热和压制层叠对准的连接板，使得连接导体或连接导体和导体电路彼此导电连接，并且连接板通过绝缘树脂组合物层彼此机械连接。 连接板通过特定的加工形成，包括使用三层复合金属层。

公开(公告)号：US07696439B2

公开(公告)日：2010-04-13

申请号：US11801336

申请日：2007-05-09

Applicant: David Light

Inventor： David Light

IPC: H01B7/18 ,  H05K1/00

CPC classification number: H05K3/062 ,  H05K3/202 ,  H05K2201/0361 ,  H05K2203/0384 ,  Y10T29/49224

Abstract: A layered metal structure is provided in accordance with an aspect of the invention. The structure can be used, for example, to fabricate a conductive interconnect element for conductively interconnecting one or more microelectronic elements. The layered structure includes first and second metal layers each of which may include one or more of copper or aluminum, for example. An intervening layer, may include for example, chromium between the first and second metal layers, chromium being resistant to an etchant usable to pattern the first and second metal layers selectively to the intervening layer. An etchant such as cupric chloride, ferric chloride (FeCl3), a peroxysulfuric composition, or a persulfate composition may be used to pattern the first and second metal layers in such case.

Abstract translation: 根据本发明的一个方面提供了层状金属结构。 该结构可以用于例如制造导电互连一个或多个微电子元件的导电互连元件。 层状结构包括例如可以包括铜或铝中的一种或多种的第一和第二金属层。 中间层可以包括例如在第一和第二金属层之间的铬，铬耐腐蚀剂可以选择性地将第一和第二金属层图案化成中间层。 在这种情况下，可以使用诸如氯化铜，氯化铁（FeCl 3），过氧化硫组合物或过硫酸盐组合物的蚀刻剂来图案化第一和第二金属层。

公开(公告)号：US20090294401A1

公开(公告)日：2009-12-03

申请号：US12129689

申请日：2008-05-30

Applicant: Chang-Fu Chen

Inventor： Chang-Fu Chen

IPC: H01B13/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/81136 ,  H01L2224/81801 ,  H05K3/06 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4652 ,  H05K3/4682 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2203/0353 ,  H05K2203/0384 ,  Y10T29/49155 ,  Y10T29/49169

Abstract: A method of fabricating a packaging substrate is disclosed. A cladding sheet comprised of a first metal foil, a second metal foil and an etch stop layer interposed between the first and second metal foils is provided. The first metal foil is then patterned into a first circuit trace. An insulating layer is laminated onto the first circuit trace. Thereafter, the second metal foil is patterned into a plurality of bump pads. The etch stop layer that is not covered by the bump pads is stripped off. A solder mask is applied to fill the spacing between the bump pads. A top surface of each of the bump pads is etched to form a bonding aperture in a self-aligned fashion.

Abstract translation: 公开了一种制造封装衬底的方法。 提供由第一金属箔，第二金属箔和介于第一和第二金属箔之间的蚀刻停止层构成的覆层片。 然后将第一金属箔图案化成第一电路迹线。 绝缘层被层压到第一电路迹线上。 此后，将第二金属箔图案化成多个凸块焊盘。 剥离不被凸块焊接的蚀刻停止层被剥离。 施加焊接掩模以填充凸块之间的间隔。 每个凸块焊盘的顶表面被蚀刻以自对准的方式形成接合孔。

公开(公告)号：US07247938B2

公开(公告)日：2007-07-24

申请号：US10510588

申请日：2003-04-10

Applicant: Roelf Anco Jacob Groenhuis ,  Paul Dijkstra ,  Cornelis Gerardus Schriks ,  Peter Wilhelmus Maria Van De Water

Inventor： Roelf Anco Jacob Groenhuis ,  Paul Dijkstra ,  Cornelis Gerardus Schriks ,  Peter Wilhelmus Maria Van De Water

IPC: H01L23/04

CPC classification number: H05K3/062 ,  A23G3/366 ,  A23G4/123 ,  A23L33/135 ,  A23Y2220/77 ,  A61K35/747 ,  C12R1/225 ,  H01L21/4828 ,  H01L21/4832 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/185 ,  H05K2201/0361 ,  H05K2203/0384 ,  H05K2203/1469 ,  H05K2203/1476 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The carrier (30) comprises a first etch mask (14), a first metal layer (11), an intermediate layer (12), a second metal layer (13) and a second etch mask (17). Both the first and the second etch mask (14, 17) can be provided in one step by means of electrochemical plating. After the first metal layer (11) and the intermediate layer (12) have been patterned through the first etch mask (14), an electric element (20) can be suitably attached to the carrier (30) using conductive means. In this patterning operation, the intermediate layer (12) is etched further so as to create underetching below the first metal layer (11). After the provision of an encapsulation (40), the second metal layer (13) is patterned through the second etch mask (17). In this manner, a solderable device (10) is obtained without a photolithographic step during the assembly process.

Abstract translation: 载体（30）包括第一蚀刻掩模（14），第一金属层（11），中间层（12），第二金属层（13）和第二蚀刻掩模（17）。 可以通过电化学电镀在一个步骤中提供第一和第二蚀刻掩模（14,17）。 在通过第一蚀刻掩模（14）对第一金属层（11）和中间层（12）进行了图案化之后，可以使用导电装置将电气元件（20）适当地附接到载体（30）。 在该图案化操作中，进一步蚀刻中间层（12），以便在第一金属层（11）的下面产生不规则的凹凸。 在提供封装（40）之后，第二金属层（13）通过第二蚀刻掩模（17）构图。 以这种方式，在组装过程中获得无可光刻步骤的可焊接装置（10）。

公开(公告)号：US07152315B1

公开(公告)日：2006-12-26

申请号：US10826019

申请日：2004-04-17

Applicant: Mohan R. Paruchuri

Inventor： Mohan R. Paruchuri

IPC: H05K3/20

CPC classification number: H05K3/44 ,  H05K3/4038 ,  H05K3/445 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A method 10, 80, 81 for making multi-layer electronic circuit boards 77, 137, 139 having metallized apertures 18, 20, 34, 40, 104, 106, 120.

Abstract translation: 一种用于制造具有金属化孔18,20,34,40,104,106,120的多层电子电路板77,137,139的方法10,80,81。

公开(公告)号：US06585903B1

公开(公告)日：2003-07-01

申请号：US09655985

申请日：2000-09-06

Applicant: Robert Edward Belke, Jr. ,  Vivek A. Jairazbhoy ,  Thomas B. Krautheim ,  William F. Quitty, Jr.

Inventor： Robert Edward Belke, Jr. ,  Vivek A. Jairazbhoy ,  Thomas B. Krautheim ,  William F. Quitty, Jr.

IPC: C23F100

CPC classification number: H05K3/44 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2201/09745 ,  H05K2201/0979 ,  H05K2201/09854 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49156

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics by causing a first insulating layer to separate from a portion of a first conductive layer of the multi-layer electronic circuit board 10 which allows for communication by and between some or all of the various component containing surfaces, and portions of the formed multi-layer electrical circuit board 10, which selectively allows components contained within and/or upon these portions and surfaces to be interconnected.

Abstract translation: 多层电子电路板设计10具有选择性地形成的孔或空腔26，其通过使第一绝缘层与多层电子电路板10的第一导电层的一部分分离而具有改善的焊料润湿特性，其允许 用于与部分或全部各种部件容纳表面之间进行通信，以及形成的多层电路板10的部分，其选择性地允许包含在这些部分和表面内部和/或之上的部件互连。

公开(公告)号：US06499214B2

公开(公告)日：2002-12-31

申请号：US09812449

申请日：2001-03-20

Applicant: Delin Li ,  Richard Keith McMillan ,  Zhong-You Shi

Inventor： Delin Li ,  Richard Keith McMillan ,  Zhong-You Shi

IPC: H05K320

CPC classification number: H05K3/429 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A method 10, 110 for making multi-layer circuit boards having metallized apertures 38, 40, 130, 132 which may be selectively and electrically grounded and having at least one formed air-bridge 92, 178.

Abstract translation: 一种用于制造具有金属化孔38,40,130,132的多层电路板的方法10,110，其可以选择性地和电接地并且具有至少一个形成的空气桥92,178。

公开(公告)号：US06495053B1

公开(公告)日：2002-12-17

申请号：US09651765

申请日：2000-08-30

Applicant: Lawrence Leroy Kneisel ,  Mohan R. Paruchuri ,  Vivek Amir Jalrazbhoy ,  Vladimir Stoica

Inventor： Lawrence Leroy Kneisel ,  Mohan R. Paruchuri ,  Vivek Amir Jalrazbhoy ,  Vladimir Stoica

IPC: H01B124

CPC classification number: H05K3/4641 ,  H05K3/386 ,  H05K3/4038 ,  H05K3/445 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2201/09581 ,  H05K2203/1438

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.

Abstract translation: 具有选择性地形成的孔或空腔26的多层电子电路板设计10，并且其包括槽或槽20,22，其有效地选择性地捕获液化的粘合剂材料，从而基本上防止粘合剂材料进入孔26。

公开(公告)号：US20020166840A1

公开(公告)日：2002-11-14

申请号：US10184968

申请日：2002-07-01

Applicant: TOYO KOHAN CO., LTD.

Inventor： Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida

IPC: B32B003/00

CPC classification number: H05K3/062 ,  H05K3/20 ,  H05K3/44 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2203/0384 ,  H05K2203/0733 ,  Y10S428/901 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/12931 ,  Y10T428/12944 ,  Y10T428/24917

Abstract: In the present invention, which produces a clad sheet for a multilayered printed circuit board capable of being economically manufactured and having excellent performance, a multilayered printed circuit board using thereof and a manufacturing method thereof, a multilayered printed circuit board is manufactured by forming clad sheet for a multilayered printed circuit board 34 by laminating copper foil 19, 24, 33 which are to be formed into conductor layer 10, 17, 18 and nickel plating 20, 21 which are to be etching-stopper layer and simultaneously press-bonding both, producing a base by selectively etching clad sheet for a multilayered printed circuit board 34, forming outer conductor layer 15, 16 on the surface of the base and simultaneously making patterning, and electrically connecting among conductor layer 10, 15, 16 by interposing columnar conductor 17, 18 formed by etching copper foil 19, 24, 33 and nickel plating 20, 21.

Abstract translation: 在本发明中，其制造能够经济地制造并具有优异性能的多层印刷电路板用复合板，使用其的多层印刷电路板及其制造方法，多层印刷电路板通过形成包覆层 对于多层印刷电路板34，通过将要形成导体层10,17,18和作为蚀刻停止层并同时压接两者的镍镀层20,21的铜箔19,24,33层压， 通过选择性地蚀刻用于多层印刷电路板34的包覆片来形成基底，在基底的表面上形成外部导体层15,16并同时进行构图，并且通过插入柱状导体17将导体层10,15,16电连接 18，通过蚀刻铜箔19,24,33和镀镍20,21形成。