公开(公告)号：US08462092B2

公开(公告)日：2013-06-11

申请号：US12830455

申请日：2010-07-06

Applicant: Li-Chih Hsu ,  Peng-Bo Xi ,  Chia-Chiang Hsiao

Inventor： Li-Chih Hsu ,  Peng-Bo Xi ,  Chia-Chiang Hsiao

IPC: G09G3/36

CPC classification number: G09G3/006 ,  G09G3/3648 ,  G09G2300/0443

Abstract: A display panel includes at least twelve sub-pixels, arranged continuously in a row. In a scanning time of the display panel, sub-pixels respectively disposed at a 2nd, 3rd, 5th, 8th, 10th and 12th column have a first polarity, and sub-pixels respectively disposed at a 1st, 4th, 6th, 7th, 9th and 11th column have a second polarity. The first polarity is opposite to the second polarity.

Abstract translation: 显示面板包括至少十二个子像素，连续排成一列。 在显示面板的扫描时间中，分别设置在第2，第3，第5，第8，第10，第12列的子像素具有第一极性，分别设置在第1，第4，第6，第7，第9 第11列具有第二极性。 第一极性与第二极性相反。

公开(公告)号：US20120262430A1

公开(公告)日：2012-10-18

申请号：US13167689

申请日：2011-06-23

Applicant: Sheng-Ju Ho ,  Cheng-Han Tsao ,  Chung-Yi Chiu ,  Chao-Yuan Chen ,  Wen-Hao Hsu ,  Peng-Bo Xi

Inventor： Sheng-Ju Ho ,  Cheng-Han Tsao ,  Chung-Yi Chiu ,  Chao-Yuan Chen ,  Wen-Hao Hsu ,  Peng-Bo Xi

IPC: G09G5/00 ,  H01L33/36

CPC classification number: H04N13/359 ,  G02F1/13624 ,  G09G3/003 ,  G09G3/3659 ,  G09G5/18 ,  G09G2300/0426 ,  G09G2300/0852 ,  G09G2310/06

Abstract: A pixel array, a pixel structure, and a driving method of a pixel structure are provided. The pixel structure includes a first scan line, a second scan line, a first common electrode line, a data line, a first active device, a second device, a first pixel electrode, and a second pixel electrode. The data line is intersected with the first scan line and the second scan line. The first active device is driven by the first scan line and connected to the data line. The second active device is driven by the second scan line and connected to the first common electrode line. The first pixel electrode is electrically connected to the data line through the first active device. The second pixel electrode is electrically connected to the data line through the first active device and electrically connected to the first common electrode line through the second active device.

Abstract translation: 提供像素阵列，像素结构以及像素结构的驱动方法。 像素结构包括第一扫描线，第二扫描线，第一公共电极线，数据线，第一有源器件，第二器件，第一像素电极和第二像素电极。 数据线与第一条扫描线和第二条扫描线相交。 第一个有源器件由第一条扫描线驱动并连接到数据线。 第二有源器件由第二扫描线驱动并连接到第一公共电极线。 第一像素电极通过第一有源器件电连接到数据线。 第二像素电极通过第一有源器件电连接到数据线，并通过第二有源器件电连接到第一公共电极线。

公开(公告)号：US20120081273A1

公开(公告)日：2012-04-05

申请号：US13040273

申请日：2011-03-04

Applicant: Ya-Ling Hsu ,  Peng-Bo Xi ,  Hung-Lung Hou

Inventor： Ya-Ling Hsu ,  Peng-Bo Xi ,  Hung-Lung Hou

IPC: G09G3/20

CPC classification number: G02F1/1362 ,  G02F2001/136218

Abstract: A pixel structure, a pixel array, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a pixel electrode, and a conductive bar pattern. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The conductive bar pattern is located on and electrically connected to the data line. The conductive bar pattern has a line width greater than or equal to a line width of the data line, and the conductive bar pattern and the pixel electrode are in the same layer.

Abstract translation: 提供像素结构，像素阵列和显示面板。 像素结构包括扫描线，数据线，有源器件，像素电极和导电棒图案。 有源器件电连接到扫描线和数据线。 像素电极电连接到有源器件。 导电棒图案位于数据线上并与之电连接。 导电棒图形具有大于或等于数据线的线宽的线宽，并且导电棒图案和像素电极处于同一层。

公开(公告)号：US20120026447A1

公开(公告)日：2012-02-02

申请号：US13017033

申请日：2011-01-30

Applicant: Peng-Bo Xi ,  Shin-Hung Yeh ,  Wei-Kai Huang ,  Ya-Ling Hsu

Inventor： Peng-Bo Xi ,  Shin-Hung Yeh ,  Wei-Kai Huang ,  Ya-Ling Hsu

IPC: G02F1/1343

CPC classification number: G02F1/136213

Abstract: A pixel structure includes at least one first sub-pixel electrode, at least one second sub-pixel electrode, at least one common line, at least one first transistor electrically connected to the first sub-pixel electrode, and at least one second transistor electrically connected to the second sub-pixel electrode. The common line overlaps and is coupled respectively with the first sub-pixel electrode and the second sub-pixel electrode so as to respectively form a first storage capacitor and a second storage capacitor. The second storage capacitor is larger than the first storage capacitor. A first adjusting capacitor of the first transistor is larger than a second adjusting capacitor of the second transistor.

Abstract translation: 像素结构包括至少一个第一子像素电极，至少一个第二子像素电极，至少一个公共线，至少一个电连接到第一子像素电极的第一晶体管，以及至少一个第二晶体管， 连接到第二子像素电极。 公共线重叠并分别与第一子像素电极和第二子像素电极耦合，以分别形成第一存储电容器和第二存储电容器。 第二存储电容器大于第一存储电容器。 第一晶体管的第一调整电容器大于第二晶体管的第二调整电容器。

公开(公告)号：US20090283822A1

公开(公告)日：2009-11-19

申请号：US12122150

申请日：2008-05-16

Applicant: WAN TENG HSIEH ,  I HSUAN LIAO ,  SHIH FANG CHEN ,  TING CHANG CHANG ,  PENG BO XI ,  WEI REN CHEN

Inventor： WAN TENG HSIEH ,  I HSUAN LIAO ,  SHIH FANG CHEN ,  TING CHANG CHANG ,  PENG BO XI ,  WEI REN CHEN

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L29/7881 ,  H01L29/42332

Abstract: A non-volatile memory structure includes a substrate having two doped regions, a charge-trapping structure positioned substantially between the two doped regions, and a conductive structure positioned on the charge-trapping structure, wherein the charge-trapping structure includes a silicon-oxy-nitride layer and metallic nano-dots embedded in the silicon-oxy-nitride layer. The non-volatile memory structure formed by performing a first thermal oxidation process to form a high-k dielectric layer on a substrate, forming a metal-containing semiconductor layer including silicon or germanium on the high-k dielectric layer, forming a silicon layer on the metal-containing semiconductor layer, and performing a second thermal oxidation process to convert the metal-containing semiconductor layer to a silicon-oxy-nitride layer with embedded metallic nano-dots, wherein at least one of the first thermal oxidation process and the second thermal oxidation process is performed in a nitrogen-containing atmosphere.

Abstract translation: 非易失性存储器结构包括具有两个掺杂区域的基底，基本上位于两个掺杂区域之间的电荷俘获结构，以及位于电荷俘获结构上的导电结构，其中电荷俘获结构包括硅 - 氧 氮化物层和嵌入在硅 - 氮化物层中的金属纳米点。 通过进行第一热氧化处理以在衬底上形成高k电介质层而形成的非易失性存储结构，在高k电介质层上形成包含硅或锗的含金属的半导体层，形成硅层 所述含金属的半导体层，并且进行第二热氧化工艺以将含金属的半导体层转换成具有嵌入的金属纳米点的硅 - 氮化物层，其中所述第一热氧化工艺和所述第二热氧化工艺中的至少一个 在含氮气氛中进行热氧化处理。