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11.发明申请公开(公告)号：US20250123766A1
公开(公告)日：2025-04-17
申请号：US18987464
申请日：2024-12-19
Applicant: STMicroelectronics France
Inventor： Zouhaier AOUAINI , Haithem RAHMANI
Abstract: System, method, and circuitry for simulating a memory architecture to generate a bin image of a file tree for a memory embedded on a programmable computing device. A memory configuration of the memory and a file tree identifying a file structure to be used in the memory are obtained. A bin image of a file system for the memory is generated based on the memory configuration and the file tree using a memory simulator and a file-management-system manager. The bin image is provided to the programmable computing device for storage in the memory.
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公开(公告)号：US12249991B2
公开(公告)日：2025-03-11
申请号：US18345726
申请日：2023-06-30
Applicant: STMicroelectronics France
Inventor： Laurent Jean Garcia , Marc Houdebine
IPC: H03K3/03 , H03K5/1252
Abstract: A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.
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公开(公告)号：US20240413228A1
公开(公告)日：2024-12-12
申请号：US18809567
申请日：2024-08-20
Applicant: STMicroelectronics France
Inventor： Philippe GALY
IPC: H01L29/739 , H10B41/40
Abstract: A cell includes a Z-PET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.
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公开(公告)号：US12167142B2
公开(公告)日：2024-12-10
申请号：US17808667
申请日：2022-06-24
Inventor： Arnaud Bourge , Tanguy Le Dauphin , Antoine Drouot , Brian Douglas Stewart
Abstract: In an embodiment an apparatus includes a scanning photographic sensor configured to acquire an image, according to an integration time of the sensor, of a scene illuminated with periodically emitted light pulses by a source, so that the image has a regular succession of bands with different luminosities when the integration time of the sensor is different from a period of the light pulses, a processor configured to generate a signature vector representative of the regular succession of bands with different luminosities being present in the image acquired by the photographic sensor, wherein the signature vector is independent of a reflectance of an objects of the scene and of a level of light in the scene, determine a frequency of the bands in the image on basis of the generated signature vector and determine the period of the pulses of the source on basis of the determined frequency of the bands in the image, and a controller configured to adjust the integration time of the photographic sensor so that the integration time is a multiple of the determined period of the light pulses of the source.
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公开(公告)号：US20240385808A1
公开(公告)日：2024-11-21
申请号：US18744311
申请日：2024-06-14
Applicant: STMicroelectronics France
Inventor： Tarek BOCHKATI
IPC: G06F8/30
Abstract: System, method, and circuitry for generating a linker model for use by a toolchain associated with a programmable computing device. One or more regions in the memory resources available to the programmable computing devices is defined for used by an application executing on the programmable computing device. One or more sections is defined for those regions for use by the application. Resource boundaries are generated for the application based on the defined regions and the defined sections. A user is enabled to modify the defined regions or the defined sections or the generated resource boundaries. A linker model is then generated based on the available memory resources, the defined regions, the defined sections, and the generated resource boundaries. This linker model is then utilized to generate a linker script for the programmable computing device based the linker syntax compatible with a toolchain linker for the programmable computing device.
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Patent Agency Ranking
公开(公告)号：US12081286B2
公开(公告)日：2024-09-03
申请号：US16587419
申请日：2019-09-30
Inventor： Francois Agut , Severin Trochut , Vinko Kunc
CPC classification number: H04B5/24 , G06K19/0725 , G08C17/02 , H02M3/33576
Abstract: A reader is adapted to wirelessly exchanging information with a wireless apparatus. The reader includes a signal generator configured to generate a modulation signal. An emitter/receptor stage is configured to be driven by the modulation signal. A switched-mode power supply is configured to power the emitter/receptor stage. The switched-mode power supply includes a power switch controlled in function of the modulation signal.
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17.发明公开公开(公告)号：US20240232549A9
公开(公告)日：2024-07-11
申请号：US18486373
申请日：2023-10-13
Applicant: STMicroelectronics France
Inventor： Florent Sibille , Marc Houdebine
CPC classification number: G06K7/10297 , H04L7/0331
Abstract: In one embodiment, an object can communicate contactlessly with a reader using active load modulation. The method includes detecting a sensing magnetic field emitted by the reader, initializing a phase-locked loop of the object, detecting a stopping of the sensing magnetic field emitted by the reader before initializing the phase-locked loop of the object is complete, calibrating an oscillator of the phase-locked loop on the basis of an internal clock of the object, detecting a new sensing magnetic field of the reader after calibrating the oscillator, and implementing the phase-locked loop to adjust the phase of the oscillator after detecting a new sensing magnetic field.
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18.发明公开公开(公告)号：US20240178053A1
公开(公告)日：2024-05-30
申请号：US18514770
申请日：2023-11-20
Inventor： Houssein El Dirani , Marouane Mastari , Mohamed Ali Nsibi
IPC: H01L21/762 , H01L23/522
CPC classification number: H01L21/76224 , H01L23/5226 , H01L23/5227
Abstract: The integrated circuit includes a semiconductor substrate having a front face including isolation structures that extend vertically into the substrate from the front face as far as a first depth, and an interconnection part comprising metal levels incorporating at least one passive component, above the front face of the substrate. The integrated circuit further includes a dielectric structure that is vertically aligned with the position of the at least one passive component, and that extends vertically into the substrate from the front face as far as a second depth that is greater than the first depth.
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公开(公告)号：US11907156B2
公开(公告)日：2024-02-20
申请号：US17457553
申请日：2021-12-03
Applicant: STMicroelectronics France , STMicroelectronics (Alps) SAS
Inventor： Michael Soulie , Thomas Martin
CPC classification number: G06F15/7807 , G06F1/08 , G06F1/14
Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.
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公开(公告)号：US11895417B2
公开(公告)日：2024-02-06
申请号：US17667485
申请日：2022-02-08
Applicant: STMicroelectronics France , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Crolles 2) SAS
Inventor： Celine Mas , Matteo Maria Vignetti , Francois Agut
IPC: H04N25/709 , H04N25/75 , H01L27/146
CPC classification number: H04N25/709 , H04N25/75 , H01L27/1463 , H01L27/14609
Abstract: The present description describes an image sensor including an array of pixels arranged inside and on top of a region of a semiconductor substrate electrically insulated from the rest of the substrate by insulating trenches crossing the substrate, each pixel including a photoconversion area and at least two assemblies, each including a memory area and a transfer gate coupling the memory area to the photoconversion area, and a circuit configured to apply, for each pixel and at least during each integration phase, a bias voltage different from ground to a portion of the substrate having the pixel arranged inside and on top of it.
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