公开(公告)号：US20240353907A1

公开(公告)日：2024-10-24

申请号：US18640103

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunjeong KIM ,  Takahiro Nomiyama

IPC: G06F1/28 ,  G06F1/08 ,  G06F1/14

CPC classification number: G06F1/28 ,  G06F1/08 ,  G06F1/14

Abstract: A system-on-chip includes a functional circuit, a voltage droop detection circuit, a clock generation circuit, and a clock modulation. The voltage droop detection circuit includes a voltage droop detection controller, a reference voltage generator, and a detection signal generator.

公开(公告)号：US12117864B2

公开(公告)日：2024-10-15

申请号：US17951113

申请日：2022-09-23

Applicant: Global Unichip Corporation ,  Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bi-Yang Li ,  Igor Elkanovich ,  Hung-Yi Chang ,  Shih-Cheng Kao

IPC: G06F1/08 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F13/42 ,  H03K3/012 ,  H03K3/037 ,  H03K5/00 ,  H03K5/22

CPC classification number: G06F1/08 ,  G06F1/12 ,  H03K3/012 ,  H03K3/0372 ,  H03K5/22 ,  G06F1/04 ,  G06F1/10 ,  G06F13/4217 ,  G06F13/423 ,  H03K2005/00019

Abstract: An interface device and a signal transceiving method thereof are provided. The interface device includes a master circuit and a slave circuit. The slave circuit includes a second receiver, a clock generator, a sampler, and a comparator. The first receiver and second receiver respectively receive input data and a clock signal from the master circuit. The clock generator delays the clock signal according to a delay value to generate a delayed clock signal, and generates a plurality of sampling signals according to the delayed clock signal. The sampler samples the input data according to the sampling signals to generate a plurality of sampling results. The comparator compares the sampling results to generate a comparison result. The clock generator adjusts the delay value according to the comparison result.

公开(公告)号：US12111684B2

公开(公告)日：2024-10-08

申请号：US18455101

申请日：2023-08-24

Applicant: International Business Machines Corporation

Inventor： Douglas J. Malone ,  Andreas H. A. Arp ,  Franklin M. Baez ,  Daniel M. Dreps ,  Jason Lee Frankel ,  Chad Andrew Marquart ,  Ching Lung Tong ,  Lily Jielu Zhang

IPC: G06F1/12 ,  G06F1/08 ,  H03L7/085

CPC classification number: G06F1/12 ,  G06F1/08 ,  H03L7/085

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

公开(公告)号：US12103406B2

公开(公告)日：2024-10-01

申请号：US18161974

申请日：2023-01-31

Applicant: Delphi Technologies IP Limited

Inventor： Mark Wendell Gose ,  Seyed R. Zarabadi ,  David Paul Buehler ,  Kevin M. Gertiser

IPC: B60L50/51 ,  B60L3/00 ,  B60L15/00 ,  B60L15/08 ,  B60L50/40 ,  B60L50/60 ,  B60L50/64 ,  B60L53/20 ,  B60L53/22 ,  B60L53/62 ,  B60R16/02 ,  G01R15/20 ,  G06F1/08 ,  G06F13/40 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/367 ,  H01L23/373 ,  H01L23/40 ,  H01L23/467 ,  H01L23/473 ,  H01L23/495 ,  H01L23/538 ,  H01L25/00 ,  H01L25/07 ,  H01L29/66 ,  H02J7/00 ,  H02M1/00 ,  H02M1/08 ,  H02M1/084 ,  H02M1/088 ,  H02M1/12 ,  H02M1/32 ,  H02M1/42 ,  H02M1/44 ,  H02M3/335 ,  H02M7/00 ,  H02M7/537 ,  H02M7/5387 ,  H02M7/5395 ,  H02P27/06 ,  H02P27/08 ,  H02P29/024 ,  H02P29/68 ,  H05K1/14 ,  H05K1/18 ,  H05K5/02 ,  H05K7/20 ,  B60L15/20 ,  H03K19/20

CPC classification number: B60L50/60 ,  B60L3/003 ,  B60L15/007 ,  B60L15/08 ,  B60L50/40 ,  B60L50/51 ,  B60L50/64 ,  B60L53/20 ,  B60L53/22 ,  B60L53/62 ,  B60R16/02 ,  G01R15/20 ,  G06F1/08 ,  G06F13/4004 ,  H01L21/4882 ,  H01L23/15 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/3735 ,  H01L23/4006 ,  H01L23/467 ,  H01L23/473 ,  H01L23/49562 ,  H01L23/5383 ,  H01L24/32 ,  H01L24/33 ,  H01L25/072 ,  H01L25/50 ,  H01L29/66553 ,  H02J7/0063 ,  H02M1/0009 ,  H02M1/0054 ,  H02M1/08 ,  H02M1/084 ,  H02M1/088 ,  H02M1/123 ,  H02M1/32 ,  H02M1/322 ,  H02M1/327 ,  H02M1/4258 ,  H02M1/44 ,  H02M3/33523 ,  H02M7/003 ,  H02M7/537 ,  H02M7/5387 ,  H02M7/53871 ,  H02M7/53875 ,  H02M7/5395 ,  H02P27/06 ,  H02P27/08 ,  H02P27/085 ,  H02P29/024 ,  H02P29/027 ,  H02P29/68 ,  H05K1/145 ,  H05K1/181 ,  H05K1/182 ,  H05K5/0247 ,  H05K7/20154 ,  H05K7/2049 ,  H05K7/20854 ,  H05K7/209 ,  H05K7/20927 ,  B60L15/20 ,  B60L2210/30 ,  B60L2210/40 ,  B60L2210/42 ,  B60L2210/44 ,  B60L2240/36 ,  G06F2213/40 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H02J2207/20 ,  H02P2207/05 ,  H03K19/20 ,  H05K2201/042 ,  H05K2201/10166

Abstract: A system includes: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a first power module including: a first connection; a second connection; a first power switch including a first gate terminal, the first power switch configured to control a first flow of current between the first connection and the second connection based on a first signal to the first gate terminal; and a first point-of-use controller configured to provide the first signal to the first gate terminal to control the first power switch.

公开(公告)号：US20240319762A1

公开(公告)日：2024-09-26

申请号：US18731170

申请日：2024-05-31

Applicant: GOWIN Semiconductor Corporation

Inventor： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC: G06F1/10 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F30/34 ,  G06F30/396

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F30/34 ,  G06F30/396

Abstract: A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

公开(公告)号：US12099378B2

公开(公告)日：2024-09-24

申请号：US17963129

申请日：2022-10-10

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Ravi Jenkal ,  Donghyun Kim

IPC: G06F1/08 ,  G06F1/3206 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/08 ,  G06F1/3206 ,  G06F9/3877 ,  G06F9/4837 ,  G06F9/4843

Abstract: Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

公开(公告)号：US12094553B2

公开(公告)日：2024-09-17

申请号：US17556363

申请日：2021-12-20

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

IPC: G11C7/22 ,  G01R23/02 ,  G06F13/16 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50 ,  H03L1/02 ,  G01R23/15 ,  G01R35/00 ,  G06F1/08 ,  G06F1/12 ,  G06F11/16 ,  G11C7/04

CPC classification number: G11C29/50012 ,  G01R23/02 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  H03L1/02 ,  G01R23/15 ,  G01R35/005 ,  G06F1/08 ,  G06F1/12 ,  G06F11/1604 ,  G11C7/04 ,  G11C2207/2254

Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

公开(公告)号：US12086427B2

公开(公告)日：2024-09-10

申请号：US17677641

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F1/28 ,  G06F1/08 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/08 ,  G06F1/28 ,  G06F3/0653 ,  G06F3/0673

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US20240296363A1

公开(公告)日：2024-09-05

申请号：US18599043

申请日：2024-03-07

Applicant: Universal Quantum Ltd

Inventor： Richard NORTH

IPC: G06N10/20 ,  G06F1/08 ,  G06F1/12

CPC classification number: G06N10/20 ,  G06F1/08 ,  G06F1/12

Abstract: According to the invention, there is provided a timing system for an ion trap quantum computer comprising a clock outputting a timing signal of period t, a plurality of delay lines coupled to the clock and each configured to input a different delay of less than t and a delay selection mechanism configured to select the delay wherein the delay by each of the delay lines is a different fraction of the period t.

公开(公告)号：US12081200B2

公开(公告)日：2024-09-03

申请号：US17938948

申请日：2022-09-07

Applicant: Nuvoton Technology Corporation

Inventor： Chun-Wei Lin

IPC: G06F1/04 ,  G06F1/08 ,  H03K3/037 ,  H03K17/00 ,  H03K19/20

CPC classification number: H03K17/005 ,  G06F1/04 ,  G06F1/08 ,  H03K3/037 ,  H03K19/20

Abstract: Provided is a clock switching device including a first latch circuit, a second latch circuit, and a switching circuit. The first latch circuit latches a first selection signal based on triggering of a first clock signal. The second latch circuit latches a second selection signal based on triggering of a second clock signal. A reset terminal of the second latch circuit is coupled to the first latch circuit. The second latch circuit is selectively reset based on an output of the first latch circuit. The switching circuit is coupled to an output terminal of the first latch circuit and an output terminal of the second latch circuit. The switching circuit selects one of the clock signals as an output clock signal of the clock switching device based on the selection signals.