公开(公告)号：US09258014B2

公开(公告)日：2016-02-09

申请号：US14543641

申请日：2014-11-17

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/00 ,  H03M13/37 ,  H03M13/13 ,  H04L1/00 ,  G06F11/10 ,  G06F12/02 ,  G06F12/06 ,  H03M13/11 ,  H03M13/15

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0683 ,  G06F11/1092 ,  G06F11/1096 ,  G06F12/0238 ,  G06F12/06 ,  G06F2211/1057 ,  G06F2211/109 ,  H03M13/11 ,  H03M13/1191 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/154 ,  H03M13/158 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/3776 ,  H03M13/616 ,  H04L1/0043

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Abstract translation: 提供了一种用于在第一存储器中使用ECC数据的软件纠错码（ECC）保护或压缩原始数据的系统。 该系统包括用于执行计算机指令和从主存储器访问数据的处理核心以及用于存储计算机指令的非易失性存储介质。 软件ECC保护或压缩包括：用于将原始数据保存在第一存储器中的数据矩阵; 用于将ECC数据保存在第一存储器中的校验矩阵; 用于在主存储器中保存第一因子的编码矩阵，第一因素是将原始数据编码到ECC数据中; 以及用于在处理核上执行的线程。 线程包括用于将数据矩阵的条目乘以编码矩阵的条目的伽罗瓦域乘法器，以及用于使用伽罗瓦域乘法器排序操作以生成ECC数据的定序器。

公开(公告)号：US09160374B2

公开(公告)日：2015-10-13

申请号：US14223740

申请日：2014-03-24

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/00 ,  H03M13/37 ,  H03M13/13 ,  H04L1/00 ,  G06F11/10 ,  G06F12/02 ,  G06F12/06 ,  H03M13/15 ,  H03M13/11

CPC classification number: H03M13/154 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1092 ,  G06F11/1096 ,  G06F12/0238 ,  G06F12/06 ,  G06F2211/1057 ,  G06F2211/109 ,  G11C29/52 ,  H03M13/1191 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/3776 ,  H03M13/616 ,  H03M13/6502 ,  H04L1/0043 ,  H04L1/0057

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Abstract translation: 加速擦除编码系统包括用于执行计算机指令并从主存储器访问数据的处理核心和用于存储计算机指令的非易失性存储介质。 处理核心，存储介质和计算机指令被配置为实现擦除编码系统，其包括：用于在主存储器中保存原始数据的数据矩阵; 用于在主存储器中保持校验数据的校验矩阵; 用于在主存储器中保存第一因子的编码矩阵，第一因素是用于将原始数据编码到检查数据中; 以及用于在处理核上执行的线程。 线程包括：并行乘法器，用于将数据矩阵的多个条目同时乘以编码矩阵的单个条目; 以及用于通过数据矩阵排序操作的第一定序器和使用并行乘法器的编码矩阵来生成检查数据。

公开(公告)号：US20150207522A1

公开(公告)日：2015-07-23

申请号：US14543641

申请日：2014-11-17

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/11 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0683 ,  G06F11/1092 ,  G06F11/1096 ,  G06F12/0238 ,  G06F12/06 ,  G06F2211/1057 ,  G06F2211/109 ,  H03M13/11 ,  H03M13/1191 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/154 ,  H03M13/158 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/3776 ,  H03M13/616 ,  H04L1/0043

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Abstract translation: 提供了一种用于在第一存储器中使用ECC数据的软件纠错码（ECC）保护或压缩原始数据的系统。 该系统包括用于执行计算机指令和从主存储器访问数据的处理核心以及用于存储计算机指令的非易失性存储介质。 软件ECC保护或压缩包括：用于将原始数据保存在第一存储器中的数据矩阵; 用于将ECC数据保存在第一存储器中的校验矩阵; 用于在主存储器中保存第一因子的编码矩阵，第一因素是将原始数据编码到ECC数据中; 以及用于在处理核上执行的线程。 线程包括用于将数据矩阵的条目乘以编码矩阵的条目的伽罗瓦域乘法器，以及用于使用伽罗瓦域乘法器排序操作以生成ECC数据的定序器。

公开(公告)号：US11848686B2

公开(公告)日：2023-12-19

申请号：US17747828

申请日：2022-05-18

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/11 ,  H03M13/00 ,  H03M13/03 ,  H04L1/1812 ,  H04L1/00 ,  H03M13/15 ,  G06F15/80 ,  G06F9/48 ,  G06F9/50

CPC classification number: H03M13/1575 ,  G06F9/4881 ,  G06F9/5027 ,  G06F15/8007 ,  H03M13/154 ,  H03M13/6516

Abstract: A system using accelerated error-correcting code in the storage and retrieval of data, wherein a single-instruction-multiple-data (SIMD) processor, SIMD instructions, non-volatile storage media, and an I/O controller implement a polynomial coding system including: a data matrix including at least one vector and including rows of at least one block of original data; a check matrix including more than two rows of at least one block of check data in the main memory; and a thread that executes on a SIMD CPU core and including: a parallel multiplier that multiplies the at least one vector of the data matrix by a single factor; and a parallel linear feedback shift register (LFSR) sequencer or a parallel syndrome sequencer configured to order load operations of the original data into at least one vector register of the SIMD CPU core and respectively compute the check data or syndrome data with the parallel multiplier.

公开(公告)号：US20200295784A1

公开(公告)日：2020-09-17

申请号：US16855910

申请日：2020-04-22

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/15 ,  G06F11/10 ,  H03M13/11 ,  H03M13/13 ,  G06F12/02 ,  G06F12/06 ,  H03M13/37 ,  H04L1/00 ,  H03M13/00 ,  G11C29/52

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

公开(公告)号：US20200250035A1

公开(公告)日：2020-08-06

申请号：US16855901

申请日：2020-04-22

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: G06F11/10 ,  H03M13/15 ,  G06F3/06 ,  H03M13/11 ,  H03M13/37 ,  H04L1/00 ,  G06F12/02 ,  G06F12/06 ,  H03M13/13 ,  H03M13/00

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

公开(公告)号：US10291259B2

公开(公告)日：2019-05-14

申请号：US15976175

申请日：2018-05-10

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/15 ,  G06F11/10 ,  H03M13/11 ,  H03M13/13 ,  G06F12/02 ,  G06F12/06 ,  H03M13/37 ,  H03M13/00 ,  H04L1/00 ,  G11C29/52

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

公开(公告)号：US20180323806A1

公开(公告)日：2018-11-08

申请号：US16036206

申请日：2018-07-16

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/15 ,  H03M13/00 ,  H03M13/09

CPC classification number: H03M13/1595 ,  H03M13/091 ,  H03M13/1515 ,  H03M13/1575 ,  H03M13/158 ,  H03M13/6561

Abstract: A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison.

公开(公告)号：US09760439B2

公开(公告)日：2017-09-12

申请号：US15018782

申请日：2016-02-08

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/37 ,  H03M13/15 ,  H03M13/13 ,  G06F12/06 ,  G06F12/02 ,  H04L1/00 ,  H03M13/11 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0683 ,  G06F11/1092 ,  G06F11/1096 ,  G06F12/0238 ,  G06F12/06 ,  G06F2211/1057 ,  G06F2211/109 ,  H03M13/11 ,  H03M13/1191 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/154 ,  H03M13/158 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/3776 ,  H03M13/616 ,  H04L1/0043

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

公开(公告)号：US20160072525A1

公开(公告)日：2016-03-10

申请号：US14852438

申请日：2015-09-11

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/15 ,  H03M13/00

CPC classification number: H03M13/154 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1092 ,  G06F11/1096 ,  G06F12/0238 ,  G06F12/06 ,  G06F2211/1057 ,  G06F2211/109 ,  G11C29/52 ,  H03M13/1191 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/3776 ,  H03M13/616 ,  H03M13/6502 ,  H04L1/0043 ,  H04L1/0057

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.