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    Accelerated erasure coding system and method
    1.
    发明授权
    Accelerated erasure coding system and method 有权

    公开(公告)号：US12199637B2

    公开(公告)日：2025-01-14

    申请号：US18213766

    申请日：2023-06-23

    Applicant: STREAMSCALE, INC.

    Inventor： Michael H. Anderson

    IPC: H03M13/15 ,  G06F11/10 ,  G06F12/02 ,  G06F12/06 ,  G11C29/52 ,  H03M13/00 ,  H03M13/11 ,  H03M13/13 ,  H03M13/37 ,  H04L1/00

    Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

    Using parity data for concurrent data authentication, correction, compression, and encryption
    4.
    发明授权
    Using parity data for concurrent data authentication, correction, compression, and encryption 有权

    公开(公告)号：US10268544B2

    公开(公告)日：2019-04-23

    申请号：US15701111

    申请日：2017-09-11

    Applicant: STREAMSCALE, INC.

    Inventor： Michael H. Anderson

    IPC: G06F11/10 ,  H03M13/00 ,  H03M13/37 ,  H03M13/15 ,  H03M13/13 ,  G06F12/06 ,  G06F12/02 ,  H04L1/00 ,  H03M13/11 ,  G06F3/06

    Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

    ACCELERATED ERASURE CODING SYSTEM AND METHOD
    6.
    发明申请
    ACCELERATED ERASURE CODING SYSTEM AND METHOD 有权
    加速擦除编码系统及方法

    公开(公告)号：US20150012796A1

    公开(公告)日：2015-01-08

    申请号：US14223740

    申请日：2014-03-24

    Applicant: STREAMSCALE, INC.

    Inventor： Michael H. Anderson ,  Sarah Mann

    IPC: H03M13/00 ,  H03M13/37

    CPC classification number: H03M13/154 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1092 ,  G06F11/1096 ,  G06F12/0238 ,  G06F12/06 ,  G06F2211/1057 ,  G06F2211/109 ,  G11C29/52 ,  H03M13/1191 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/3776 ,  H03M13/616 ,  H03M13/6502 ,  H04L1/0043 ,  H04L1/0057

    Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

    Abstract translation: 加速擦除编码系统包括用于执行计算机指令和从主存储器访问数据的处理核心和用于存储计算机指令的非易失性存储介质。 处理核心，存储介质和计算机指令被配置为实现擦除编码系统，其包括：用于在主存储器中保存原始数据的数据矩阵; 用于在主存储器中保持校验数据的校验矩阵; 用于在主存储器中保存第一因子的编码矩阵，第一因素是用于将原始数据编码到检查数据中; 以及用于在处理核上执行的线程。 线程包括：并行乘法器，用于将数据矩阵的多个条目同时乘以编码矩阵的单个条目; 以及用于通过数据矩阵排序操作的第一定序器和使用并行乘法器的编码矩阵来生成检查数据。

    SLIDING WINDOW LIST DECODER FOR ERROR CORRECTING CODES
    9.
    发明申请
    SLIDING WINDOW LIST DECODER FOR ERROR CORRECTING CODES 审中-公开

    公开(公告)号：US20170317692A1

    公开(公告)日：2017-11-02

    申请号：US15650806

    申请日：2017-07-14

    Applicant: STREAMSCALE, INC.

    Inventor： Michael H. Anderson

    IPC: H03M13/09 ,  H03M13/15 ,  H03M13/00

    CPC classification number: H03M13/1595 ,  H03M13/091 ,  H03M13/1515 ,  H03M13/1575 ,  H03M13/158 ,  H03M13/6561

    Abstract: A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison.

    Sliding window list decoder for error correcting codes
    10.
    发明授权
    Sliding window list decoder for error correcting codes 有权

    公开(公告)号：US09722632B2

    公开(公告)日：2017-08-01

    申请号：US14492685

    申请日：2014-09-22

    Applicant: Streamscale, Inc.

    Inventor： Michael H. Anderson

    IPC: H03M13/09 ,  H03M13/15 ,  H03M13/00

    CPC classification number: H03M13/1595 ,  H03M13/091 ,  H03M13/1515 ,  H03M13/1575 ,  H03M13/158 ,  H03M13/6561

    Abstract: A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison.

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