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公开(公告)号：US5963496A
公开(公告)日：1999-10-05
申请号：US64811
申请日：1998-04-22
Applicant: Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
Inventor： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
CPC classification number: G11C7/062 , G11C7/065 , G11C7/1036
Abstract: A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.
Abstract translation: 用于串行配置存储器的读出放大器包括响应于控制脉冲以控制器方式启用和禁用的多个级。 在外部提供的时钟信号的每第N个周期产生控制脉冲，该时钟用于计时表示存储器件的内容的比特流。 在优选实施例中，N个这样的感测放大器用于并行地读出构成访问的存储器位置的N个存储器单元（位）。 因此，感测放大器仅在足以读出存储器单元的一段时间内是有效的。
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公开(公告)号：US5946267A
公开(公告)日：1999-08-31
申请号：US978286
申请日：1997-11-25
Applicant: Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
Inventor： Saroj Pathak , Glen A. Rosendale , James E. Payne , Nianglamching Hangzo
CPC classification number: G11C7/1039
Abstract: A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.
Abstract translation: 串行配置存储器件包括以流水线方式执行读出数据和输出比特流的架构。 结果，该装置能够仅基于外部提供的时钟的频率输出比特流，并且不受感测放大器电路的较慢的操作速度的限制。 提供了一种缓存方案，其允许在复位周期期间预加载第一字节，使得一旦复位周期完成，设备就可以立即开始输出比特流。 在本发明的优选实施例中，比特流由从存储器位置零开始的串行访问的存储器位置组成。 在一个变型中，比特流可以从除存储器位置零之外的存储器位置开始。
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公开(公告)号：US5917754A
公开(公告)日：1999-06-29
申请号：US859885
申请日：1997-05-21
Applicant: Saroj Pathak , Jagdish Pathak
Inventor： Saroj Pathak , Jagdish Pathak
Abstract: A memory device includes a memory cell whose data state is sensed by a sense amplifier. A balance amplifier having the same construction as the sense amplifier is utilized to sense a balance cell having the same construction as the memory cell. The balance cell is maintained in an erased (conductive) state. The balance cell is gated by the output of the sense amplifier. Such a device operates in a way to consume the same amount of power regardless of the data state of the memory cell. In one embodiment of the invention, a memory device consisting of a memory array includes a balance circuit associated with each of the sense amplifiers in the memory device. In another embodiment of the invention, a trim circuit is used to adjust the conductivity of the of the balance circuit. This allows the balance circuit to be fine tuned during manufacture to compensate for process variations, thus allowing the balance circuit to be matched to the memory cells.
Abstract translation: 存储器件包括其读出放大器检测其数据状态的存储单元。 使用具有与读出放大器相同结构的平衡放大器来感测与存储单元具有相同结构的平衡单元。 平衡电池保持在擦除（导电）状态。 平衡单元由读出放大器的输出选通。 无论存储器单元的数据状态如何，这种器件都以消耗相同的功率量的方式工作。 在本发明的一个实施例中，由存储器阵列组成的存储器件包括与存储器件中每个读出放大器相关联的平衡电路。 在本发明的另一个实施例中，使用微调电路来调节平衡电路的电导率。 这允许平衡电路在制造期间被微调以补偿过程变化，从而允许平衡电路与存储器单元匹配。
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公开(公告)号：US5493244A
公开(公告)日：1996-02-20
申请号：US180689
申请日：1994-01-13
Applicant: Saroj Pathak , James E. Payne , Glen A. Rosendale
Inventor： Saroj Pathak , James E. Payne , Glen A. Rosendale
IPC: H03K17/0814 , H03K17/10 , H03K17/687 , H03K17/693 , H03K19/003 , H03K5/08
CPC classification number: H03K17/693 , H03K17/08142 , H03K17/102 , H03K19/00315 , H03K19/00361 , H01L2924/0002
Abstract: A high voltage circuit includes a first switching device for supplying one of a high voltage (V.sub.pp) and a low voltage (V.sub.cc) to a controlled path that includes a series connection of a control p-channel transistor and a protection p-channel transistor. A high voltage detector is utilized to determine whether V.sub.pp or V.sub.cc is applied to the controlled path. The high voltage detector also establishes a protecting condition for the protection p-channel transistor during V.sub.pp operation. On the other hand, the detector establishes a non-protecting condition during V.sub.cc operation, thereby rendering the protecting p-channel transistor transparent to circuit performance. A signal input switches the control p-channel transistor between on and off states. When the control transistor is in an off state and the protection transistor is in a protecting condition, the voltage drop along the controlled path will cause the protection transistor to turn off, so as to limit the voltage across the control transistor. A second controlled path is preferably in series connection with the first controlled path. The second controlled path includes n-channel transistors, with one of the transistors fixed at V.sub.cc in order to guard against gate-aided junction breakdown of the other transistor. In this embodiment, the high voltage circuit is preferably an inverter circuit.
Abstract translation: 高压电路包括用于将高电压（Vpp）和低电压（Vcc）中的一个提供给包括控制p沟道晶体管和保护p沟道晶体管的串联连接的受控路径的第一开关器件。 利用高电压检测器来确定是否将Vpp或Vcc应用于受控路径。 高电压检测器还在Vpp操作期间为保护p沟道晶体管建立了保护条件。 另一方面，检测器在Vcc操作期间建立非保护状态，从而使得保护p沟道晶体管对电路性能是透明的。 信号输入在控制p沟道晶体管的导通和截止状态之间切换。 当控制晶体管处于断开状态并且保护晶体管处于保护状态时，沿受控路径的电压降将导致保护晶体管截止，从而限制控制晶体管两端的电压。 第二受控路径优选地与第一受控路径串联连接。 第二受控路径包括n沟道晶体管，其中一个晶体管固定在Vcc，以防止另一个晶体管的栅极辅助结击穿。 在本实施例中，高压电路优选为逆变器电路。
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公开(公告)号：US5272674A
公开(公告)日：1993-12-21
申请号：US948481
申请日：1992-09-21
Applicant: Saroj Pathak , Glen A. Rosendale
Inventor： Saroj Pathak , Glen A. Rosendale
CPC classification number: G11C7/02 , G11C16/26 , G11C7/067 , G11C7/1006
Abstract: A read circuit for a semiconductor memory that includes a pass transistor between the output of a first sense amplifier reading the memory and a latch. The pass transistor blocks transmission of the sense amplifier's output to the latch whenever a noise glitch producing condition is sensed. A second sense amplifier connected through the same conductive line to the memory cell array as the first sense amplifier has a faster response and lower current threshold in order to detect the glitch producing condition. A pulse generator receives the output of the second sense amplifier and provides a control signal pulse of predetermined duration following detection of the glitch producing condition by the second sense amplifier. The pulse is received by a control gate of the pass transistor, turning the transistor off during the duration of the pulse.
Abstract translation: 一种用于半导体存储器的读取电路，其包括在读取存储器的第一读出放大器的输出端与锁存器之间的传输晶体管。 每当检测到噪声毛刺产生条件时，传递晶体管阻止读出放大器的输出到锁存器的传输。 通过与第一读出放大器相同的导线连接到存储单元阵列的第二读出放大器具有更快的响应和更低的电流阈值，以便检测毛刺产生状况。 脉冲发生器接收第二读出放大器的输出，并在由第二读出放大器检测到毛刺产生状态之后提供预定持续时间的控制信号脉冲。 脉冲由传输晶体管的控制栅极接收，在脉冲持续时间内关断晶体管。
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Patent Agency Ranking
16.发明授权公开(公告)号：US06320454B1
公开(公告)日：2001-11-20
申请号：US09586664
申请日：2000-06-01
Applicant: Saroj Pathak , James E. Payne , Harry H. Kuo
Inventor： Saroj Pathak , James E. Payne , Harry H. Kuo
IPC: G05F110
CPC classification number: G05F1/465
Abstract: A voltage regulator circuit that receives an input signal and provides an output signal that is clamped at a specified voltage desired for an internal circuit. The disclosed voltage regulator circuit includes a plurality of subcircuits including a voltage tracking subcircuit in which the output voltage tracks the input voltage with no voltage drop when the input voltage starts to rise from zero volts. If the input voltage increases to a desired voltage level for the internal circuit, the voltage tracking subcircuit clamps the output voltage to remain at that voltage. If the input voltage further increases to a higher voltage, the voltage tracking subcircuit is disabled and one of a plurality of voltage maintaining subcircuit takes control so that the output voltage remains at the desired voltage for the internal circuit.
Abstract translation: 电压调节器电路，其接收输入信号并提供被钳位在内部电路所需的指定电压下的输出信号。 所公开的电压调节器电路包括多个子电路，其包括电压跟踪子电路，其中当输入电压从零伏开始上升时，输出电压跟踪输入电压而没有电压降。 如果输入电压增加到内部电路的所需电压电平，则电压跟踪分支电路将输出电压钳位以保持在该电压。 如果输入电压进一步增加到较高的电压，则电压跟踪子电路被禁止，并且控制多个电压保持子电路中的一个，使得输出电压保持在内部电路的期望电压。
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17.发明授权
公开(公告)号：US6140993A
公开(公告)日：2000-10-31
申请号：US97866
申请日：1998-06-16
Applicant: Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
Inventor： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
CPC classification number: G09G3/3688 , G09G3/3677 , G09G2300/0876 , G09G2310/0289 , G09G3/2011 , G09G3/2074
Abstract: A circuit for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor powered by a high voltage power source to bias a pass transistor at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.
Abstract translation: 用于传送高压模拟视频信号同时能够使用常规低电压逻辑电平的电路包括由高电压电源供电的第一晶体管，以在高电压电平下偏置传输晶体管。 传输晶体管接收高电压视频信号，并且由于高电压偏压能够通过视频信号而不会由于馈通效应而导致信号衰减，从而保持视频信号的保真度。 第二晶体管提供接地电位，其操作以关闭传输晶体管，从而禁止视频信号通过其传输。 可操作地耦合到第一晶体管的第三晶体管操作以在第二晶体管工作时关断第一晶体管。
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公开(公告)号：US6115305A
公开(公告)日：2000-09-05
申请号：US333805
申请日：1999-06-15
Applicant: Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
Inventor： Saroj Pathak , James E. Payne , Glen A. Rosendale , Nianglamching Hangzo
CPC classification number: G11C29/02 , G01R31/31855
Abstract: A video chip includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register. There is a circuit for the column lines and for the row lines. A bit pattern is driven onto the column or the row lines and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.
Abstract translation: 视频芯片包括用于检测开路和短路的测试电路。 该电路包括串联连接的晶体管链和测试寄存器。 列线和行线都有一个电路。 位模式被驱动到列或行线上并被接收在相应的测试电路中。 该模式被读出并与输入模式进行比较以检测故障线路。
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公开(公告)号：US5781469A
公开(公告)日：1998-07-14
申请号：US788523
申请日：1997-01-24
Applicant: Saroj Pathak , James E. Payne
Inventor： Saroj Pathak , James E. Payne
IPC: G11C11/41 , G11C11/419 , G11C7/00
CPC classification number: G11C11/419
Abstract: An SRAM configures its bitline load structure to implement one of three different precharge schemes, none of which use an ATD circuit. The SRAM monitors its WRITE/READ pin and initiates a first precharging scheme when the SRAM is in a read mode. In the first precharging scheme, every complementary bitline pair is directly coupled to Vcc via a first pmos transistor which is permanently turned on, regardless of whether a memory cell is being read or not. Additionally, both true and false bitlines in every complementary bitline pair are coupled together via a pmos transistor as long as the SRAM remains in a read mode. When in a write mode, the second precharging scheme is initiated causing the second pmos transistor to be turned off and only the first pmos transistors remain active. Thus, all complementary bitline pairs which are not selected for a write operation are pulled up to Vcc by the first pmos transistors. The termination of the write mode activates the third precharging scheme which causes all the bitlines, both true and false, within the memory array to be momentarily shorted together. The cumulative equivalent capacitance of the complementary bitlines pairs which were not selected for a write operation help to pull up the few complementary bitlines pairs which were pull down during the previous write operation.
Abstract translation: SRAM配置其位线负载结构以实现三种不同的预充电方案中的一种，其中一种不使用ATD电路。 当SRAM处于读取模式时，SRAM监视其写入/读取引脚并启动第一个预充电方案。 在第一预充电方案中，不管存储器单元是否被读取，每个互补位线对都经由永久地导通的第一个pmos晶体管直接耦合到Vcc。 另外，只要SRAM保持在读取模式，每个互补位线对中的真位和错位都通过pmos晶体管耦合在一起。 当处于写入模式时，启动第二预充电方案，使第二个pmos晶体管截止，并且只有第一个pmos晶体管保持有效。 因此，未被选择用于写操作的所有互补位线对被第一pmos晶体管上拉至Vcc。 写入模式的终止激活第三个预充电方案，这导致存储器阵列内的所有位线都为真和假，以便短暂地短路。 补充位线对的累积等效电容未被选择用于写入操作有助于拉出在之前的写入操作期间被拉低的少数互补位线对。
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公开(公告)号：US5731734A
公开(公告)日：1998-03-24
申请号：US726956
申请日：1996-10-07
Applicant: Jagdish Pathak , James E. Payne , Saroj Pathak
Inventor： Jagdish Pathak , James E. Payne , Saroj Pathak
IPC: H01L21/8238 , G11C29/04 , H01L21/82 , H01L27/092 , H03K3/356 , H03K17/687
CPC classification number: H03K3/356008 , H03K3/356182
Abstract: A zero power fuse circuit includes a latch means having two inputs, a first input being latched to ground and a second input being latched to V.sub.cc. The latch means is triggered either by a momentary contact of the first input to ground or by the momentary contact of the second input to V.sub.cc. A first embodiment includes two fuse element/capacitor pairs each coupled to one of the two inputs of the latch means. A second embodiment includes a pull-up transistor and a fuse element/capacitor pair, coupled to the first and second inputs respectively. A third embodiment includes a pull-down transistor and a fuse element/capacitor pair respectively coupled to the second and first inputs of the latch means.
Abstract translation: 零功率熔断器电路包括具有两个输入的锁存装置，第一输入端被锁存到地，第二输入端被锁存到Vcc。 闩锁装置通过第一输入端与地之间的瞬时接触或第二输入端瞬间接触到Vcc来触发。 第一实施例包括每个耦合到锁存装置的两个输入之一的两个熔丝元件/电容器对。 第二实施例包括分别耦合到第一和第二输入的上拉晶体管和熔丝元件/电容器对。 第三实施例包括分别耦合到锁存装置的第二和第一输入端的下拉晶体管和熔丝元件/电容器对。
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