公开(公告)号：US4978905A

公开(公告)日：1990-12-18

申请号：US429722

申请日：1989-10-31

Applicant: David Hoff ,  Saroj Pathak

Inventor： David Hoff ,  Saroj Pathak

IPC: G05F3/24 ,  H03K17/14 ,  H03K17/16

CPC classification number: G05F3/247 ,  G05F3/245 ,  H03K17/145 ,  H03K17/163 ,  Y10S323/907

Abstract: A circuit for compensating for MOS device response to supply voltage variations, as well as temperature and process variations, in an integrated circuit device. The compensation circuit produces a reference voltage which modulates the gate bias voltage of a MOS transistor such that the gate-to-source bias of the MOS transistor is varied to compensate for variations in the supply voltage as well as for variations in the temperature and manufacturing process. The circuit pulls up the reference voltage toward the supply voltage as the supply increases, thereby increasing the gate drive on the MOS transistor. The circuit provides compensation for both AC and DC supply variations. The MOS transistor is used to modulate the available current sinking capability in an IC device output buffer, such that as the MOS gate drive increases, the current sinking capability is reduced, thereby slowing the output state transitions as the supply increases, and reducing noise caused by supply variations.

Abstract translation: 用于补偿MOS器件对集成电路器件中的电压变化以及温度和工艺变化的响应的电路。 补偿电路产生参考电压，其调制MOS晶体管的栅极偏置电压，使得MOS晶体管的栅极 - 源极偏置被改变以补偿电源电压的变化以及温度和制造的变化 处理。 当电源增加时，电路将电压提升到电源电压，从而增加了MOS晶体管上的栅极驱动。 该电路为交流和直流电源变化提供补偿。 MOS晶体管用于调制IC器件输出缓冲器中的可用电流吸收能力，使得当MOS栅极驱动器增加时，电流吸收能力降低，从而随着电源增加而减慢输出状态转换，并降低噪声 通过供应变化。

公开(公告)号：US06476785B1

公开(公告)日：2002-11-05

申请号：US09436064

申请日：1999-11-08

Applicant: Saroj Pathak ,  James E. Payne

Inventor： Saroj Pathak ,  James E. Payne

IPC: G05B1942

CPC classification number: G09G3/3659 ,  G09G2300/0814 ,  G09G2300/0842 ,  G09G2300/0852

Abstract: A driver circuit for use in an array of picture elements in a liquid crystal display is capable of displaying one set of image data while receiving a second set of image data. A first select switch transistor responsive to a first select signal controls the coupling of a first image to a first storage capacitor. A second select switch transistor responsive to a second select signal controls the coupling of a second image to a second storage capacitor. The first storage capacitor may be selectively coupled to an output node by means of a first enable switch transistor responsive to a first enable signal. The second storage capacitor may be selectively coupled to the same output node by means of a second enable switch transistor responsive to a second enable signal. By proper manipulation of the switch transistors, one storage capacitor may be coupled to the output node while the other storage capacitor is isolated from the output node and receiving new image data.

Abstract translation: 用于液晶显示器中的像素阵列的驱动电路能够在接收第二组图像数据的同时显示一组图像数据。 响应于第一选择信号的第一选择开关晶体管控制第一图像与第一存储电容器的耦合。 响应于第二选择信号的第二选择开关晶体管控制第二图像与第二存储电容器的耦合。 可以通过响应于第一使能信号的第一使能开关晶体管将第一存储电容器选择性地耦合到输出节点。 第二存储电容器可以通过响应于第二使能信号的第二使能开关晶体管选择性地耦合到相同的输出节点。 通过对开关晶体管的适当操作，一个存储电容器可以耦合到输出节点，而另一个存储电容器与输出节点隔离并接收新的图像数据。

公开(公告)号：US5999038A

公开(公告)日：1999-12-07

申请号：US160526

申请日：1998-09-24

Applicant: Saroj Pathak ,  James E. Payne

Inventor： Saroj Pathak ,  James E. Payne

IPC: G11C17/18 ,  G11C17/16 ,  G11C29/00 ,  H01H20060101 ,  H01H37/76 ,  H01H85/00 ,  H01H85/044 ,  H01H85/46 ,  H01L21/82 ,  H01L21/822 ,  H01L27/00 ,  H01L27/04 ,  H03K17/56 ,  H03K19/003

CPC classification number: G11C17/18

Abstract: A fuse circuit includes a fusible element and a feedback path which causes the circuit to behave as if the fusible element is fully blown even though the fusible element in fact is partially intact. While a partially intact fuse normally would result in a continuous drain of power, the feedback path cuts off the current flow through the partially intact fusible element.

Abstract translation: 熔丝电路包括可熔元件和反馈路径，其使得电路的行为就好像即使可熔元件实际上是部分完整的，易熔元件完全熔断。 虽然部分完整的保险丝通常会导致功率的持续耗尽，但反馈路径切断了通过部分完整的可熔元件的电流。

公开(公告)号：US5936444A

公开(公告)日：1999-08-10

申请号：US977779

申请日：1997-11-25

Applicant: Jagdish Pathak ,  Saroj Pathak ,  Glen A. Rosendale ,  James E. Payne ,  Nianglamching Hangzo

Inventor： Jagdish Pathak ,  Saroj Pathak ,  Glen A. Rosendale ,  James E. Payne ,  Nianglamching Hangzo

IPC: H03K17/22

CPC classification number: H03K17/223

Abstract: A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.

Abstract translation: 上电复位电路包括用于在加电期间建立电荷的第一充电阶段。 感测第一充电阶段的上升电压并用于控制用于对第二充电阶段充电的装置。 当第二充电阶段达到第一电压电平时，电路跳闸以将第一至第二电荷的电位拉到地。 第一充电阶段的接地被反馈到充电装置，其关闭其功率燃烧部件并在第二充电阶段保持第一电压电平。

公开(公告)号：US06809550B2

公开(公告)日：2004-10-26

申请号：US10251402

申请日：2002-09-20

Applicant: Saroj Pathak ,  James E. Payne ,  Victor V. Nguyen ,  Harry H. Kuo

Inventor： Saroj Pathak ,  James E. Payne ,  Victor V. Nguyen ,  Harry H. Kuo

IPC: H03K19177

CPC classification number: H03K19/1776 ,  G11C16/0433 ,  G11C16/26 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17784

Abstract: A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path with inverter, and an output logic gate. The single path is coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.

Abstract translation: 可编程逻辑器件（PLD）架构包括多个PLD单位逻辑单元。 每个单个位逻辑单元由包括可编程单元单元，可设置锁存器，具有反相器的信号路径和输出逻辑门的所有CMOS逻辑器件组成。 单路径耦合到单元单元，可设置锁存器和输出逻辑门，以产生正反馈环路，以提高速度和噪声抗扰度。 每个单位逻辑门是用于模块化低功耗，高速，零直流电流，高抗噪声可编程逻辑器件（PLD）的基本构建块，其包括排列成行和列的阵列，用于寻址 ，或门阵列，以及多个输出逻辑电路。

公开(公告)号：US06411549B1

公开(公告)日：2002-06-25

申请号：US09602108

申请日：2000-06-21

Applicant: Saroj Pathak ,  James E. Payne ,  Jagdish Pathak

Inventor： Saroj Pathak ,  James E. Payne ,  Jagdish Pathak

IPC: G11C1606

CPC classification number: G11C16/28 ,  G11C7/067 ,  G11C7/14

Abstract: A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.

Abstract translation: 用于高速感测电路的参考单元包括第一子电路和第二子电路。 第一子电路具有类似于主存储器阵列的奇数行内的存储单元的结构。 第二子电路具有类似于主存储器阵列的偶数行内的存储单元的结构。 如果主存储器阵列内的目标单元位于奇数行内，则选择第一子电路，并且如果目标单元位于偶数行中，则选择第二子电路。 第一和第二子电路都包括其控制门分成两部分的参考晶体管。 第一部分是聚1层，并且通过隧道氧化物与沟道区分离。 第二部分是在第一部分上的金属或聚二层，并且通过栅极氧化物与第一部分分离。 通孔用于将第一部分连接到第二部分。

公开(公告)号：US5440508A

公开(公告)日：1995-08-08

申请号：US194930

申请日：1994-02-09

Applicant: Saroj Pathak ,  James E. Payne

Inventor： Saroj Pathak ,  James E. Payne

IPC: G11C17/00 ,  G11C14/00 ,  G11C16/04

CPC classification number: G11C14/00

Abstract: A non-volatile, low, and zero power, high speed self-sensing programmable device and architecture including a non-volatile self-sensing cell. The non-volatile self-sensing cell is connected out of the speed path of the programmable device, permitting rapid, non-volatile programming and reading operations to be conducted. According to one version, two self-sensing cells are provided with a means for selecting one of the cells for programming or read operation. Each non-volatile self-sensing cell includes a latch having cross-coupled, pull-up transistors and non-volatile pull-down cells. The cross-coupled pull-up transistors are field effect transistors having gates which are connected to the opposite sources of the cross-coupled pull-up transistors.

Abstract translation: 非易失性，低功耗和零功率的高速自感可编程器件和架构，包括非易失性自感应单元。 非易失性自感应单元被连接在可编程设备的速度路径之外，允许进行快速，非易失性的编程和读取操作。 根据一个版本，两个自感应单元被提供有用于选择一个单元以进行编程或读取操作的装置。 每个非易失性自感应单元包括具有交叉耦合的上拉晶体管和非易失性下拉单元的锁存器。 交叉耦合上拉晶体管是具有连接到交叉耦合上拉晶体管的相反源极的栅极的场效应晶体管。

公开(公告)号：US5027320A

公开(公告)日：1991-06-25

申请号：US410951

申请日：1989-09-22

Applicant: Saroj Pathak ,  Bruce Prickett

Inventor： Saroj Pathak ,  Bruce Prickett

IPC: G11C16/08

CPC classification number: G11C16/08

Abstract: The present invention relates to an MOS integrated circuit employing a plurality of floating gate type, erasable, programmable read-only memory (EPROM) devices. The improvement of the invention comprises a clamp coupled to the control gates of the EPROMs, the clamp being adapted to clamp the voltage on these gates in the range of the typical supply voltage for the circuit, whereby, after an EPROM cell is properly charged, it will continue to read out as a properly charged cell even though some of the actual charge on its floating gate may have leaked.

Abstract translation: 本发明涉及采用多个浮置型，可擦除可编程只读存储器（EPROM）器件的MOS集成电路。 本发明的改进包括耦合到EPROM的控制栅极的钳位，该钳位电路适于在电路的典型电源电压的范围内钳位这些栅极上的电压，由此在EPROM单元被适当地充电之后， 即使其浮动门上的一些实际充电可能泄漏，它仍将继续读出作为充电电池。

公开(公告)号：US4264828A

公开(公告)日：1981-04-28

申请号：US963973

申请日：1978-11-27

Applicant: George Perlegos ,  Saroj Pathak

Inventor： George Perlegos ,  Saroj Pathak

IPC: G11C8/10 ,  G11C11/408 ,  H03K19/096 ,  H03K19/094 ,  G11C8/00 ,  H03K19/017

CPC classification number: G11C11/4087 ,  G11C8/10 ,  H03K19/096

Abstract: A metal-oxide-semiconductor (MOS) static decoding circuit for selecting an addressed line in a high density memory array, or the like, is disclosed. The circuit may be laid-out along array lines where the lines have a pitch of approximately 12.25 microns. Three levels of decoding are employed. The highest level permits the pulling-up of a common node in the second level decoder. The third level of decoding selects one of a plurality of array lines coupled to this node. Zero threshold voltage MOS devices are employed for coupling the first and third decoders to the second decoder.

Abstract translation: 公开了一种用于选择高密度存储器阵列中的寻址行的金属氧化物半导体（MOS）静态解码电路等。 电路可以沿着阵列线布置，其中线具有大约12.25微米的间距。 采用三级解码。 最高级别允许在第二级解码器中提取公共节点。 第三级解码选择耦合到该节点的多个阵列线中的一个。 零阈值电压MOS器件用于将第一和第三解码器耦合到第二解码器。

公开(公告)号：US06618289B2

公开(公告)日：2003-09-09

申请号：US10039916

申请日：2001-10-29

Applicant: Saroj Pathak ,  James E. Payne ,  Harry H. Kuo

Inventor： Saroj Pathak ,  James E. Payne ,  Harry H. Kuo

IPC: G11C1606

CPC classification number: G11C16/24

Abstract: A bit/column latch comprising a pair of first and second cross-coupled CMOS inverters. Each inverter of the pair comprises an NMOS transistor and a PMOS transistor. The first CMOS inverter has the source of its NMOS transistor coupled to ground via a control transistor and has its output connected to the associated bit line. When low voltage data intended for the associated memory cell appears on the bit line, the control transistor is barely turned on to weaken the NMOS transistor of the first inverter. This makes it easier for the data on the bit line to turn on the NMOS transistor of the second inverter so as to switch the bit latch from storing a ‘low’ to storing a ‘high’. In other words, the data bit from the bit line is loaded into the bit latch. After that, the control transistor is strongly turned on and therefore it becomes transparent to the latch. As a result, the latch is stable when the bit line later ramps up to a high programming level.

Abstract translation: 一个位/列锁存器，包括一对第一和第二交叉耦合CMOS反相器。 该对的每个反相器包括NMOS晶体管和PMOS晶体管。 第一个CMOS反相器的NMOS晶体管的源极通过控制晶体管耦合到地，并且其输出连接到相关的位线。 当位于相应存储单元上的低电压数据出现在位线上时，控制晶体管几乎不导通，以削弱第一反相器的NMOS晶体管。 这使得位线上的数据更容易打开第二反相器的NMOS晶体管，以便将位锁存器从存储“低”切换到存储“高”。 换句话说，来自位线的数据位被加载到位锁存器中。 此后，控制晶体管被强烈导通，因此对锁存器变得透明。 因此，当位线稍后上升到高编程电平时，锁存器是稳定的。