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公开(公告)号：US12210365B2
公开(公告)日：2025-01-28
申请号：US16848424
申请日：2020-04-14
Applicant: Silicon Laboratories Inc.
Inventor： Mehmet Akif Altan , Steffen Skaug
Abstract: An apparatus includes an amplifier. The amplifier has two inputs, and an output. The amplifier has a pole in its transfer function. The frequency of the pole depends on the output current of the amplifier. The amplifier further includes a pole frequency tracking (PFT) circuit. The PFT circuit includes a source follower circuit.
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12.发明申请公开(公告)号：US20250024380A1
公开(公告)日：2025-01-16
申请号：US18357329
申请日：2023-07-24
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus De Ruijter
Abstract: In one aspect, a method includes: detecting, in a receiver of a wireless device, an energy of a first wireless channel; determining whether the detected energy is within a range between a first threshold and a second threshold; and in response to determining that the detected energy is within the range, transmitting, from a transmitter of the wireless device, a first radio frequency (RF) signal within the first wireless channel at a power level less than a maximum power level.
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公开(公告)号：US12193128B2
公开(公告)日：2025-01-07
申请号：US17706796
申请日：2022-03-29
Applicant: Silicon Laboratories Inc.
Inventor： Levente Kovacs
IPC: H05B47/19 , H05B47/155
Abstract: A system and method for the commissioning of a lighting system is disclosed. The lighting system includes a plurality of lighting devices and a plurality of locators. Each lighting device includes a light emitting element and a wireless tag. After the lighting system is installed, each lighting device transmits one or more packets that contain a constant tone extension (CTE). This CTE allows the locators to determine the angle of arrival of the incoming packet. By combining the angles of arrival from several locators, it is possible to ascertain the physical location of the lighting device that transmitted the CTE. In this way, the physical location of each lighting device can be correlated to its network address.
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公开(公告)号：US20250007769A1
公开(公告)日：2025-01-02
申请号：US18217015
申请日：2023-06-30
Applicant: Silicon Laboratories Inc.
Inventor： Wentao Li , Yan Zhou , Terry Lee Dickey
IPC: H04L27/26 , H04L5/00 , H04L25/497
Abstract: A receiver includes a demodulator having a configurable correlator bank that helps with fast and robust signal detection. The demodulator detects arrival of a first preamble symbol using a first correlator bank configuration. The demodulator makes a course frequency offset estimation after detection of the first preamble signal and the receiver adjusts a frequency used by a mixer based on the coarse frequency offset estimation. The demodulator confirms signal arrival detection with detection of a second preamble symbol. A coarse timing estimation is generated using a second correlator bank configuration using a multi-symbol observation period. A fine frequency offset estimation is made using a third correlation bank configuration. A fine timing estimation is made using a fourth correlation bank configuration. The demodulator then despreads received symbols using a fifth correlator bank configuration.
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公开(公告)号：US20250007643A1
公开(公告)日：2025-01-02
申请号：US18342975
申请日：2023-06-28
Applicant: Silicon Laboratories Inc.
Inventor： Fabrice Christophe Olivier Portier
IPC: H04L1/00
Abstract: In one embodiment, a transmitter includes: a circuit to generate a packet having a preamble, a header, and a data portion, where the preamble and the header are dynamically adaptable based at least in part on a range between the transmitter and a receiver; and a radio frequency (RF) front end circuit coupled to the circuit to process and transmit the packet.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20250007630A1
公开(公告)日：2025-01-02
申请号：US18344116
申请日：2023-06-29
Applicant: Silicon Laboratories Inc.
Inventor： Sriram Mudulodu , Manoj Kumar Medam
IPC: H04B17/318 , H04L27/00
Abstract: In one embodiment, a receiver includes: an analog front end (AFE) circuit to receive and process an incoming radio frequency (RF) analog signal comprising a packet; an analog-to-digital converter (ADC) coupled to the AFE circuit to receive and digitize an analog signal based on the RF analog signal into a digital signal; a packet detector coupled to the ADC to detect the packet based on the digital signal; and a computation circuit coupled to the packet detector. The computation circuit may be configured to determine a received signal strength indicator (RSSI) value based at least in part on a portion of a preamble of the packet.
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公开(公告)号：US20240429926A1
公开(公告)日：2024-12-26
申请号：US18821040
申请日：2024-08-30
Applicant: Silicon Laboratories Inc.
Inventor： John M. Khoury , Michael Wu
Abstract: A fractional-N phase-locked loop (PLL) that maintains phase coherence for an output signal with a plurality of possible output frequencies. The fractional-N PLL includes an oscillator, a phase detector to receive a reference clock signal and a feedback signal, and a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector. A multi-modulus pattern generator supplies a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal. The multi-modulus pattern generator initiates the drive pattern at a boundary time to cause the output signal to have a substantially repeatable phase when restarting switching from any one of the output frequencies to any other of the output frequencies.
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公开(公告)号：US12175118B2
公开(公告)日：2024-12-24
申请号：US17700906
申请日：2022-03-22
Applicant: Silicon Laboratories Inc.
Inventor： Thomas Saroshan David , Aslam Rafi , Joshua Norem , Adrianus Josephus Bink , Daniel Cooley
IPC: G06F3/06
Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.
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公开(公告)号：US12146935B2
公开(公告)日：2024-11-19
申请号：US17893635
申请日：2022-08-23
Applicant: Silicon Laboratories Inc.
Inventor： Anant Verma
Abstract: A system and method for performing production testing on high power semiconductor devices is disclosed. The system includes signal generators, RF meters, sockets, couplers and connectors which also function as switches when connected to an external cable. A calibration process is executed which allows the controller to create a correlation between measurements taken by the RF meter and the actual voltages, and power levels present at the device under test. By performing this calibration, it is possible to perform production testing of devices much more quickly and reliably.
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公开(公告)号：US12111407B2
公开(公告)日：2024-10-08
申请号：US17024874
申请日：2020-09-18
Applicant: Silicon Laboratories Inc.
Inventor： Lauri Mikael Hintsala
CPC classification number: G01S5/0215 , G01S5/0018 , G01S5/021 , G01S5/08 , H04L1/08 , H04W56/001 , H04W72/0446 , H04W4/80
Abstract: A system having a locator device and a plurality of tag devices is disclosed. The locator device comprises an antenna array allowing it to determine an angle of arrival for incoming signals from each of the plurality of tag devices. The system also defines a sequence of time slots, where each time slot has a specific function. The sequence may start with a locator time slot, where the locator device transmits a packet that informs all of the tag devices that this is the start of the sequence. A sync slot follows the locator time slot, where new tag devices may transmit a sync request to the locator device. Upon receipt of a sync request, the locator device assigns the new tag device a tag slot. Following the sync slot are a plurality of tag slots, where each tag device transmits an AoA packet during its assigned tag slot.
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