公开(公告)号：US20210090931A1

公开(公告)日：2021-03-25

申请号：US16578062

申请日：2019-09-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

IPC: H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A semiconductor device package includes a carrier, a patterned passivation layer and a first patterned conductive layer. The patterned passivation layer is disposed on the carrier. The first patterned conductive layer is disposed on the carrier and surrounded by the patterned passivation layer. The first patterned conductive layer has a first portion and a second portion electrically disconnected from the first portion. The first portion has a first surface adjacent to the carrier and exposed by the patterned passivation layer. The second portion has a first surface adjacent to the carrier exposed by the patterned passivation layer. The first surface of the first portion is in direct contact with an insulation medium.

公开(公告)号：US20180254238A1

公开(公告)日：2018-09-06

申请号：US15699810

申请日：2017-09-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48 ,  H05K3/34 ,  H05K1/11

CPC classification number: H01L23/49811 ,  H01L21/4832 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/113 ,  H05K3/3452 ,  H05K2201/09563 ,  H01L2924/00012 ,  H01L2224/13099

Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device. The substrate includes a first dielectric layer having a first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a conductive post. The first patterned conductive layer includes a first conductive pad and a second conductive pad. The conductive post is disposed on the first conductive pad. The conductive post includes a first portion and a second portion. The first portion and the second portion of the conductive post are exposed by the first dielectric layer. The first portion of the conductive post has a first width corresponding to a top line width of the first portion and the second portion of the conductive post has a width. The width of the second portion of the conductive post is greater than the first width of the first portion of the conductive post.

公开(公告)号：US20170301626A1

公开(公告)日：2017-10-19

申请号：US15635128

申请日：2017-06-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng LEE ,  Hsing Kuo TIEN

IPC: H01L23/538 ,  H01L21/683 ,  H01L23/13 ,  H01L23/00 ,  H01L21/48 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H01L23/36

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/36 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/215 ,  H01L2224/24145 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die.

公开(公告)号：US20170019993A1

公开(公告)日：2017-01-19

申请号：US14798384

申请日：2015-07-13

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H05K3/00 ,  H05K3/22 ,  H05K1/02 ,  H05K3/36

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

Abstract translation: 本公开涉及半导体衬底，半导体模块及其制造方法。 半导体衬底包括第一电介质结构，第二电介质结构，第一图案化导电层和第二图案化导电层。 第一电介质结构具有与第一表面相对的第一表面和第二表面。 第二电介质结构具有与第三表面相对的第三表面和第四表面，其中第四表面与第一表面相邻。 第二电介质结构限定了从第三表面延伸到第四表面的通孔。 空腔由通孔和第一电介质结构限定。 第一图案化导电层设置在第一电介质结构的第一表面上。 第二图案化导电层设置在第一介电结构的第二表面上。

公开(公告)号：US20160286645A1

公开(公告)日：2016-09-29

申请号：US15177295

申请日：2016-06-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng LEE

IPC: H05K1/11 ,  H05K3/00 ,  H05K1/02 ,  H05K3/04 ,  H05K3/06 ,  H05K3/46 ,  H05K3/10 ,  H05K3/40

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K3/0023 ,  H05K3/04 ,  H05K3/045 ,  H05K3/06 ,  H05K3/10 ,  H05K3/108 ,  H05K3/4038 ,  H05K3/4644 ,  H05K3/465 ,  H05K2201/0352 ,  H05K2203/025 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.

公开(公告)号：US20150348931A1

公开(公告)日：2015-12-03

申请号：US14700060

申请日：2015-04-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng LEE ,  Yuan Chang SU ,  Cheng-Lin HO ,  Chung-Ming WU ,  You-Lung YEN

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76801 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract translation: 本公开涉及半导体衬底，半导体封装结构及其制造方法。 一种方法包括提供衬底和载体层。 衬底包括第一图案化金属层，与第一图案化金属层间隔开的第二图案化金属层，以及设置在第一图案化金属层和第二图案化金属层之间的介电层。 电介质层覆盖第二图案化金属层。 电介质层限定暴露第二图案化金属层的第一开口，并且还限定从第一图案化金属层延伸到第二图案化金属层的通孔。 导电材料设置在通孔中并将第一图案化金属层电连接到第二图案化金属层。 载体层限定暴露第二图案化金属层的第二开口。

公开(公告)号：US20220418115A1

公开(公告)日：2022-12-29

申请号：US17899553

申请日：2022-08-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wu Chou HSU ,  Hsing Kuo TIEN ,  Chih-Cheng LEE ,  Min-Yao CHEN

IPC: H05K3/30 ,  H01L23/498 ,  H01L23/544 ,  H05K1/18 ,  H05K1/02 ,  H01L21/48

Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.

公开(公告)号：US20220115339A1

公开(公告)日：2022-04-14

申请号：US17067561

申请日：2020-10-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/49 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q1/40

Abstract: An antenna package includes a conductive layer, an interconnection structure and an antenna. The interconnection structure is disposed on the conductive layer. The interconnection structure includes a conductive via and a first package body. The conductive via has a first surface facing the conductive layer, a second surface opposite to the first surface and a lateral surface extending from the first surface to the second surface. The first package body covers the lateral surface of the conductive via and exposes the first surface and the second surface of the conductive via. The first package body is spaced apart from the conductive layer. The antenna is electrically connected to the second surface of the conductive via.

公开(公告)号：US20220028801A1

公开(公告)日：2022-01-27

申请号：US16938818

申请日：2020-07-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsing Kuo TIEN ,  Chih-Cheng LEE

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L21/48

Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, and a first circuit layer disposed on the substrate. The first circuit layer includes a conductive wiring pattern, and the conductive wiring pattern is an uppermost conductive pattern of the first circuit layer. The stress buffering structure is disposed on the first conductive structure. The second conductive structure is disposed over the stress buffering structure. The conductive wiring pattern extends through the stress buffering structure and electrically connected to the second conductive structure, and an upper surface of the conductive wiring pattern is substantially coplanar with an upper surface of the stress buffering structure.

公开(公告)号：US20210366816A1

公开(公告)日：2021-11-25

申请号：US17397842

申请日：2021-08-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.