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    SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR PACKAGE, AND METHOD FOR FORMING THE SAME
    4.
    发明申请
    SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR PACKAGE, AND METHOD FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20200279788A1

    公开(公告)日：2020-09-03

    申请号：US16878475

    申请日：2020-05-19

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

    IPC: H01L23/367 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373

    Abstract: The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.

    SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS
    5.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS 审中-公开

    公开(公告)号：US20160322292A1

    公开(公告)日：2016-11-03

    申请号：US15208569

    申请日：2016-07-12

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Yuan-Chang SU ,  Chih-Cheng LEE ,  Cheng-Lin HO

    IPC: H01L23/498

    CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/188 ,  H01L2924/00

    Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

    SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250105122A1

    公开(公告)日：2025-03-27

    申请号：US18976255

    申请日：2024-12-10

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

    ELECTRONIC PACKAGE
    7.
    发明公开
    ELECTRONIC PACKAGE 审中-公开

    公开(公告)号：US20230361014A1

    公开(公告)日：2023-11-09

    申请号：US17738768

    申请日：2022-05-06

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/528

    CPC classification number: H01L23/49822 ,  H01L23/3107 ,  H01L23/528 ,  H01L23/49827 ,  H01L23/49816 ,  H01L2224/73204 ,  H01L24/73

    Abstract: An electronic package includes an electronic structure, a first circuit pattern structure, a plurality of first solders and an encapsulant. The electronic structure includes an electronic device, and has a top surface and a bottom surface opposite to the top surface. The first circuit pattern structure is disposed over the top surface of the electronic structure. The first solders are disposed on the bottom surface of the electronic structure. The encapsulant encapsulates the electronic structure. At least a portion of the encapsulant is disposed between at least two of the plurality of first solders.

    SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS
    9.
    发明申请
    SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS 审中-公开

    公开(公告)号：US20190287867A1

    公开(公告)日：2019-09-19

    申请号：US16297451

    申请日：2019-03-08

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

    IPC: H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

    Abstract: A substrate structure includes a wiring structure and a supporter. The wiring structure includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is disposed on the first dielectric structure. The second dielectric structure covers the first dielectric structure and the first circuit layer. A pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure. The supporter is disposed adjacent to the first dielectric structure of the wiring structure, and defines at least one through hole corresponding to the exposed pad portion of the first circuit layer.

    REDUCED-DIMENSION VIA-LAND STRUCTURE AND METHOD OF MAKING THE SAME
    10.
    发明申请
    REDUCED-DIMENSION VIA-LAND STRUCTURE AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：US20170231093A1

    公开(公告)日：2017-08-10

    申请号：US15019776

    申请日：2016-02-09

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE ,  Po-Shu PENG

    IPC: H05K1/11 ,  H05K3/10 ,  H05K3/40

    CPC classification number: H05K1/116 ,  H05K3/0035 ,  H05K3/10 ,  H05K3/4038

    Abstract: A package substrate includes a dielectric layer, a conductive via disposed in the dielectric layer, and a conductive pattern layer exposed from a first surface of the dielectric layer. The conductive pattern layer includes traces and a via land, the via land extends into the conductive via, and a circumferential portion of the via land is encompassed by the conductive via. A method of making a package substrate includes forming a conductive pattern layer including traces and a via land, providing a dielectric layer to cover the conductive pattern layer, and forming a via hole. Forming the via hole is performed by removing a portion of the dielectric layer and exposing a bottom surface of the via land and at least a portion of a side surface of the via land. A conductive material is applied into the via hole to form a conductive via covering the via land.

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