公开(公告)号：US09058436B1

公开(公告)日：2015-06-16

申请号：US13682730

申请日：2012-11-20

Applicant: ALTERA Corporation

Inventor： Gordon Chiu ,  Navid Azizi

IPC: H03M7/00 ,  G06F11/30 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4009 ,  G06F11/3072 ,  G06F13/38 ,  G06F13/385 ,  G06F13/42 ,  H03M7/00

Abstract: Methods, systems and circuits for reducing aging of at least one component of a data path are disclosed. First data transmitted over a data path may be monitored in an active state to allow generation of second data, where the second data may be transmitted in an inactive state over the data path to improve the balance of any imbalance in the static probability of one logical state versus another caused by transmission of the first data. Portions of data to be transmitted over a data path may be compared to previously-transmitted portions of data to determine a respective data bus inversion (DBI) setting each portion of data, where the DBI settings may be used to increase the toggling of bits of the data path and improve the balance of the static probability of one logical state versus another.

Abstract translation: 公开了用于减少数据路径的至少一个部件的老化的方法，系统和电路。 可以在活动状态下监视通过数据路径发送的第一数据，以允许生成第二数据，其中可以通过数据路径以非活动状态发送第二数据，以改善一个逻辑的静态概率的任何不平衡的平衡 状态与另一种由第一数据的传输引起的。 可以将通过数据路径传输的数据的部分与先前发送的数据部分进行比较，以确定设置数据的每个部分的相应数据总线反相（DBI），其中DBI设置可以用于增加数据的位的翻转 数据路径，并提高一个逻辑状态与另一个逻辑状态的静态概率的平衡。

公开(公告)号：US09047215B1

公开(公告)日：2015-06-02

申请号：US13682727

申请日：2012-11-20

Applicant: ALTERA Corporation

Inventor： Gordon Chiu ,  Navid Azizi

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/33 ,  H04L12/70

CPC classification number: G06F11/108 ,  G06F11/3027 ,  G06F11/3058 ,  G06F11/3093 ,  G06F2201/88 ,  G11C7/1006 ,  H03K17/56 ,  H03K19/01728 ,  H03M13/336 ,  H04L2012/5674

Abstract: Methods, computer-readable mediums and systems for reducing transistor recovery are disclosed. Data which toggles at least one bit may be periodically communicated over a data path, where toggling of at least one bit may effectively reset the recovery period for any transistors in the data path associated with the at least one bit. Timing uncertainty associated with a given transistor may be reduced by limiting the amount of recovery experienced by the transistor. Accordingly, recovery of transistors in a data path may be limited to predetermined amount by toggling bits of the data path at a predetermined frequency, thereby reducing timing uncertainty and allowing a smaller system margin and/or higher data transmission speeds.

Abstract translation: 公开了用于减少晶体管恢复的方法，计算机可读介质和系统。 切换至少一个位的数据可以通过数据路径周期性地传送，其中至少一个位的切换可以有效地重置与至少一个位相关联的数据路径中的任何晶体管的恢复周期。 通过限制晶体管所经历的恢复量，可以减小给定晶体管的定时不确定性。 因此，可以通过以预定频率切换数据路径的位来将数据路径中的晶体管的恢复限制为预定量，从而减少定时不确定性并允许较小的系统裕度和/或更高的数据传输速度。