公开(公告)号：US20170270995A1

公开(公告)日：2017-09-21

申请号：US15614221

申请日：2017-06-05

Applicant: Altera Corporation

Inventor： Krzysztof Maryan ,  Gordon Raymond Chiu ,  Warren Nordyke ,  Navid Azizi

IPC: G11C11/4076 ,  G06F1/12 ,  G11C11/4093 ,  G11C7/10 ,  G11C8/18 ,  G11C29/02

CPC classification number: G11C11/4076 ,  G06F1/12 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4093 ,  G11C29/023

Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

公开(公告)号：US20160133309A1

公开(公告)日：2016-05-12

申请号：US14997268

申请日：2016-01-15

Applicant: Altera Corporation

Inventor： Krzysztof Maryan ,  Gordon Raymond Chiu ,  Warren Nordyke ,  Navid Azizi

IPC: G11C11/4076 ,  G06F1/12 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G06F1/12 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4093 ,  G11C29/023

Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

Abstract translation: 一方面，一种方法包括：接收包括第一和第二分量的差分选通信号; 由第一缓冲器缓冲第一和第二组分; 以及通过第二缓冲器缓冲所述第一组件。 该方法包括由控制逻辑块接收第二缓冲器的输出。 该方法包括在第一和第二分量的值处于第一逻辑状态但在差分选通信号中接收到脉冲串脉冲之前的时段之后，从第一逻辑状态检测第一分量中的转变 到第二逻辑状态，并且响应于检测到的转换，确定使能信号。 该方法还包括通过选通逻辑块接收使能信号和第一缓冲器的输出，并且当使能信号被断言时，对第一缓冲器的输出进行非门控。

公开(公告)号：US09257164B2

公开(公告)日：2016-02-09

申请号：US13829881

申请日：2013-03-14

Applicant: Altera Corporation

Inventor： Krzysztof Maryan ,  Gordon Raymond Chiu ,  Warren Nordyke ,  Navid Azizi

IPC: G11C7/10 ,  G11C29/02 ,  G11C8/18

CPC classification number: G11C11/4076 ,  G06F1/12 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4093 ,  G11C29/023

Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

Abstract translation: 一方面，一种方法包括：接收包括第一和第二分量的差分选通信号; 由第一缓冲器缓冲第一和第二组分; 以及通过第二缓冲器缓冲所述第一组件。 该方法包括由控制逻辑块接收第二缓冲器的输出。 该方法包括在第一和第二分量的值处于第一逻辑状态但在差分选通信号中接收到脉冲串脉冲之前的时段之后，从第一逻辑状态检测第一分量中的转变 到第二逻辑状态，并且响应于检测到的转换，确定使能信号。 该方法还包括通过选通逻辑块接收使能信号和第一缓冲器的输出，并且当使能信号被断言时，对第一缓冲器的输出进行非门控。

公开(公告)号：US20170359073A1

公开(公告)日：2017-12-14

申请号：US15633473

申请日：2017-06-26

Applicant: Altera Corporation

Inventor： Navid Azizi ,  Gordon Raymond Chiu ,  Michael Howard Kipper

IPC: H03K19/20 ,  G06F17/50

CPC classification number: H03K19/20 ,  G06F17/50 ,  G06F17/5045 ,  H03K19/018507

Abstract: Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.

公开(公告)号：US09698795B1

公开(公告)日：2017-07-04

申请号：US13935273

申请日：2013-07-03

Applicant: Altera Corporation

Inventor： Navid Azizi ,  Gordon Raymond Chiu ,  Michael Howard Kipper

IPC: H03K19/20 ,  G06F17/50

CPC classification number: H03K19/20 ,  G06F17/50 ,  G06F17/5045 ,  H03K19/018507

Abstract: Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.

公开(公告)号：US08977998B1

公开(公告)日：2015-03-10

申请号：US13773468

申请日：2013-02-21

Applicant: Altera Corporation

Inventor： Navid Azizi ,  Gordon Raymond Chiu ,  Ian Carlos Kuon ,  John Curtis Van Dyken

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: A method for using computing equipment to perform timing analysis on an integrated circuit design includes identifying a timing arc of the integrated circuit design. The timing arc may be a clock path or a data path in the integrated circuit design. A probability of the timing arc may be obtained and an aging effect for the timing arc may be calculated. The aging effect of the timing arc is calculated based on the probability. The timing arc may include maximum and minimum delays that are adjusted based at least partly on the calculated aging effect on the timing arc.

Abstract translation: 一种使用计算设备对集成电路设计进行定时分析的方法包括识别集成电路设计的定时弧。 定时电弧可以是集成电路设计中的时钟路径或数据路径。 可以获得定时弧的概率，并且可以计算定时弧的老化效应。 基于概率计算定时弧的老化效应。 定时弧可以包括至少部分地基于计时的对定时弧的老化效应来调整的最大和最小延迟。

公开(公告)号：US08897083B1

公开(公告)日：2014-11-25

申请号：US13715484

申请日：2012-12-14

Applicant: Altera Corporation

Inventor： Navid Azizi ,  Gordon Raymond Chiu

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/1066

Abstract: An integrated circuit may include memory interface circuitry for communicating with off-chip memory. The memory interface circuitry may receive data signals and data strobe signals from different memory devices via respective data ports and data strobe ports. The memory interface circuitry may be operable in at least first and second modes. In the first mode, data signals from each memory device may be received at two respective data ports while the data strobe signal from one memory device is used to clock the data signals at two corresponding read capture registers. In the second mode, data signals from first and second memory devices may be received via first and second data ports, respectively. The data strobe signal from the first memory device may be ignored while the data strobe signal from the second memory device is used to clock the data signals at two corresponding read capture registers.

Abstract translation: 集成电路可以包括用于与片外存储器通信的存储器接口电路。 存储器接口电路可以经由相应的数据端口和数据选通端口从不同的存储器件接收数据信号和数据选通信号。 存储器接口电路可以在至少第一和第二模式中操作。 在第一模式中，来自每个存储器件的数据信号可以在两个相应的数据端口处被接收，而来自一个存储器件的数据选通信号用于在两个对应的读取捕获寄存器上对数据信号进行时钟。 在第二模式中，可以分别经由第一和第二数据端口接收来自第一和第二存储器设备的数据信号。 可以忽略来自第一存储器件的数据选通信号，而来自第二存储器件的数据选通信号用于在两个对应的读取捕获寄存器上对数据信号进行时钟。

公开(公告)号：US09679633B2

公开(公告)日：2017-06-13

申请号：US14997268

申请日：2016-01-15

Applicant: Altera Corporation

Inventor： Krzysztof Maryan ,  Gordon Raymond Chiu ,  Warren Nordyke ,  Navid Azizi

IPC: G11C11/4076 ,  G11C7/10 ,  G11C8/18 ,  G06F1/12 ,  G11C11/4093 ,  G11C29/02

CPC classification number: G11C11/4076 ,  G06F1/12 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4093 ,  G11C29/023

Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

公开(公告)号：US20140269117A1

公开(公告)日：2014-09-18

申请号：US13829881

申请日：2013-03-14

Applicant: Altera Corporation

Inventor： Krzysztof Maryan ,  Gordon Raymond Chiu ,  Warren Nordyke ,  Navid Azizi

IPC: G11C8/18

CPC classification number: G11C11/4076 ,  G06F1/12 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4093 ,  G11C29/023

Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

Abstract translation: 一方面，一种方法包括：接收包括第一和第二分量的差分选通信号; 由第一缓冲器缓冲第一和第二组分; 以及通过第二缓冲器缓冲所述第一组件。 该方法包括由控制逻辑块接收第二缓冲器的输出。 该方法包括在第一和第二分量的值处于第一逻辑状态但在差分选通信号中接收到脉冲串脉冲之前的时间段之后，从第一逻辑状态检测第一分量中的转变 到第二逻辑状态，并且响应于检测到的转换，确定使能信号。 该方法还包括通过选通逻辑块接收使能信号和第一缓冲器的输出，并且当使能信号被断言时，对第一缓冲器的输出进行非门控。

公开(公告)号：US09948307B2

公开(公告)日：2018-04-17

申请号：US15633473

申请日：2017-06-26

Applicant: Altera Corporation

Inventor： Navid Azizi ,  Gordon Raymond Chiu ,  Michael Howard Kipper

IPC: H03K19/20 ,  G06F17/50

CPC classification number: H03K19/20 ,  G06F17/50 ,  G06F17/5045 ,  H03K19/018507

Abstract: Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.