公开(公告)号：US09983655B2

公开(公告)日：2018-05-29

申请号：US14963352

申请日：2015-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh R. Meswani ,  David A. Roberts ,  Dmitri Yudanov ,  Arkaprava Basu ,  Sergey Blagodurov

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3243 ,  G06F9/3885

Abstract: A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.

公开(公告)号：US09898287B2

公开(公告)日：2018-02-20

申请号：US14682971

申请日：2015-04-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Sooraj Puthoor ,  Bradford M. Beckmann ,  Dmitri Yudanov

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F9/30058 ,  G06F9/3804 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/46

Abstract: A method, a non-transitory computer readable medium, and a processor for repacking dynamic wavefronts during program code execution on a processing unit, each dynamic wavefront including multiple threads are presented. If a branch instruction is detected, a determination is made whether all wavefronts following a same control path in the program code have reached a compaction point, which is the branch instruction. If no branch instruction is detected in executing the program code, a determination is made whether all wavefronts following the same control path have reached a reconvergence point, which is a beginning of a program code segment to be executed by both a taken branch and a not taken branch from a previous branch instruction. The dynamic wavefronts are repacked with all threads that follow the same control path, if all wavefronts following the same control path have reached the branch instruction or the reconvergence point.

公开(公告)号：US11836610B2

公开(公告)日：2023-12-05

申请号：US15841030

申请日：2017-12-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Dmitri Yudanov ,  Nicholas Penha Malaya

IPC: G06N3/08 ,  G06N3/045

CPC classification number: G06N3/08 ,  G06N3/045

Abstract: An artificial neural network that includes first subnetworks to implement known functions and second subnetworks to implement unknown functions is trained. The first subnetworks are trained separately and in parallel on corresponding known training datasets to determine first parameter values that define the first subnetworks. The first subnetworks are executing on a plurality of processing elements in a processing system. Input values from a network training data set are provided to the artificial neural network including the trained first subnetworks. Error values are generated by comparing output values produced by the artificial neural network to labeled output values of the network training data set. The second subnetworks are trained by back propagating the error values to modify second parameter values that define the second subnetworks without modifying the first parameter values. The first and second parameter values are stored in a storage component.

公开(公告)号：US10573630B2

公开(公告)日：2020-02-25

申请号：US15958169

申请日：2018-04-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Brett P. Wilkerson ,  Milind Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

公开(公告)号：US20190333876A1

公开(公告)日：2019-10-31

申请号：US15965425

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov

IPC: H01L23/64 ,  H01L23/528 ,  H01L25/065 ,  H01L23/00 ,  H01L23/34 ,  H01L23/31

Abstract: Various chip stack power delivery circuits are disclosed. In one aspect, an apparatus is provided that includes a stack of semiconductor chips that has an uppermost semiconductor chip and a lowermost semiconductor chip. A heat spreader is positioned on the uppermost semiconductor chip. A power transfer circuit is configured to transfer electric power from the heat spreader to the uppermost semiconductor chip.

公开(公告)号：US10216454B1

公开(公告)日：2019-02-26

申请号：US15686121

申请日：2017-08-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov

IPC: G11C8/00 ,  G06F3/06 ,  G06F12/0868

Abstract: A method and apparatus of performing a memory operation includes receiving a memory operation request at a first memory controller that is in communication with a second memory controller. The first memory controller forwards the memory operation request to the second memory controller. Upon receipt of the memory operation request, the second memory controller provides first information or second information depending on a condition of a pseudo-bank of the second memory controller and a type of the memory operation request.

公开(公告)号：US10019283B2

公开(公告)日：2018-07-10

申请号：US14746601

申请日：2015-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Sergey Blagodurov ,  Arkaprava Basu ,  Sooraj Puthoor ,  Joseph L. Greathouse

IPC: G06F9/46 ,  G06F9/30

CPC classification number: G06F9/461 ,  G06F9/3013 ,  G06F9/3851

Abstract: A processing device includes a first memory that includes a context buffer. The processing device also includes a processor core to execute threads based on context information stored in registers of the processor core and a memory controller to selectively move a subset of the context information between the context buffer and the registers based on one or more latencies of the threads.

公开(公告)号：US20230350830A1

公开(公告)日：2023-11-02

申请号：US18182809

申请日：2023-03-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Michael Ignatowski

IPC: G06F13/40 ,  G11C29/44 ,  G11C29/30 ,  G06F13/16 ,  G11C5/02 ,  G11C5/06 ,  G11C5/14 ,  G11C7/06

CPC classification number: G06F13/4068 ,  G11C29/44 ,  G11C29/30 ,  G06F13/1668 ,  G11C5/02 ,  G11C5/06 ,  G11C5/147 ,  G11C7/06 ,  G11C7/1012

Abstract: An apparatus and method for performing memory operations in memory stacks comprising receiving a memory operation request at a first memory controller, where the first memory controller is in included in a first logic die in communication with a first memory die of a first memory technology, from a processor via a first bus. The method further comprising, on a condition that the memory operation request is associated with a second memory technology, communicating the memory operation request to a second memory controller via a side bus, where the second memory controller is included in a second logic die in communication with a second memory die of the second memory technology, and, on a condition that the memory operation request is associated with the first memory technology, performing the memory operation request. The first and second logic dies and the first and second memory dies being stacked on the processor.

公开(公告)号：US11604754B2

公开(公告)日：2023-03-14

申请号：US15605291

申请日：2017-05-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Michael Ignatowski

IPC: G06F13/16 ,  G06F13/40 ,  G11C29/02 ,  G11C29/30 ,  G11C29/44 ,  G11C5/02 ,  G11C5/06 ,  G11C5/14 ,  G11C7/06 ,  G11C7/10

Abstract: A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die of the first memory technology, and includes a first memory controller including a first memory control function for interpreting requests in accordance with a first protocol for the first memory technology. A second logic die is in communication with the second memory die of the second memory technology and includes a second memory controller including a second memory control function for interpreting requests in accordance with a second protocol for the second memory technology. A memory operation request is received at the first or second memory controller, and the memory operation request is performed in accordance with the associated first memory protocol or the second memory protocol.

公开(公告)号：US10713059B2

公开(公告)日：2020-07-14

申请号：US14490213

申请日：2014-09-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Joseph L. Greathouse ,  Mitesh R. Meswani ,  Sooraj Puthoor ,  Dmitri Yudanov ,  James M. O'Connor

IPC: G06F9/38

Abstract: A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.