公开(公告)号：US20150318029A1

公开(公告)日：2015-11-05

申请号：US14268183

申请日：2014-05-02

Applicant: Altera Corporation

Inventor： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC: G11C7/10 ,  G11C5/06

CPC classification number: H01L27/1104 ,  G11C5/06 ,  G11C7/1051 ,  G11C11/412 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/82345 ,  H01L29/1045 ,  H01L29/4983 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66659

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract translation: 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

公开(公告)号：US09006794B1

公开(公告)日：2015-04-14

申请号：US14164018

申请日：2014-01-24

Applicant: Altera Corporation

Inventor： Shuang Xie ,  Shankar Sinha ,  Cheng-Hsiung Huang

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit with electrically programmable fuse circuitry coupled to a programming transistor is provided. The programming transistor may be a metal-oxide-semiconductor transistor that is separated from other circuitry in an integrated circuit substrate with shallow trench isolation. The electrically programmable fuse circuitry may be formed in a second layer above the integrated circuit substrate using a conductive material which may be tungsten-based. This second layer may further include interconnect wires made from the same conductive material. The electrically programmable fuse may be coupled to the programming transistor through vias and routing paths in a fourth layer above the integrated circuit substrate. The routing paths in the fourth layer may be made from a conductive material which may be different than the fuse conductive material used to form the programmable fuse circuitry.

Abstract translation: 具有耦合到编程晶体管的电可编程熔丝电路的集成电路被提供。 编程晶体管可以是与具有浅沟槽隔离的集成电路衬底中的其它电路分离的金属氧化物半导体晶体管。 电可编程熔丝电路可以使用可以是基于钨的导电材料形成在集成电路衬底上的第二层中。 该第二层还可以包括由相同导电材料制成的互连线。 电可编程熔丝可以通过集成电路基板上方的第四层中的通孔和布线路径耦合到编程晶体管。 第四层中的布线路径可以由导电材料制成，导电材料可以不同于用于形成可编程熔丝电路的熔丝导电材料。

公开(公告)号：US20140169074A1

公开(公告)日：2014-06-19

申请号：US13715442

申请日：2012-12-14

Applicant: Altera Corporation

Inventor： Shankar Sinha ,  Brian Wong ,  Shih-Lin Lee ,  Wei Zhang ,  Abhishek Bankey Behari Sharma

IPC: G11C11/40 ,  H01L29/66

CPC classification number: H01L29/66477 ,  G11C11/412 ,  G11C11/4125 ,  H01L27/0207 ,  H01L27/1104

Abstract: Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data lines. Each of the first and second inverting circuit may have a pull-down transistor and at least two pull-up transistors stacked in series. The pull-down transistors may have body terminals that are reverse biased to help reduce leakage current through the first and second inverting circuits. The memory cell may be formed using a narrower two-gate configuration or a wider four-gate configuration.

Abstract translation: 提供具有存储单元的集成电路。 存储器单元可以包括被配置为存储单个数据位的第一和第二交叉耦合反相电路。 第一反相电路可以具有用作存储单元的第一数据存储节点的输出，而第二反相电路可以具有用作存储单元的第二数据存储节点的输出。 存取晶体管可以耦合在第一和第二数据存储节点和对应的数据线之间。 第一和第二反相电路中的每一个可以具有串联堆叠的下拉晶体管和至少两个上拉晶体管。 下拉晶体管可以具有反向偏置的主体端子，以帮助减少通过第一和第二反相电路的泄漏电流。 可以使用较窄的双栅极配置或较宽的四栅极配置来形成存储单元。