公开(公告)号：US20190250925A1

公开(公告)日：2019-08-15

申请号：US16290566

申请日：2019-03-01

Applicant: Apple Inc.

Inventor： Hardik K. Doshi

IPC: G06F9/4401 ,  G06F1/3293 ,  G06F1/3287 ,  G06F1/3203

CPC classification number: G06F9/4405 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/4418 ,  G06F9/442 ,  Y02D10/122 ,  Y02D10/171

Abstract: A computing device may comprise a first processor and a secondary processor. The first processor may initiate a power management process transitioning the first processor from a first state to a second state and, upon reaching a predetermined step in the power management process, notify the secondary processor of the power management process. The secondary processor may initiate, in response to the notifying, a parallel power management process transitioning the secondary processor from an equivalent first state to an equivalent second state.

公开(公告)号：US20180349609A1

公开(公告)日：2018-12-06

申请号：US15721502

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Joshua P. de Cesare ,  Timothy R. Paaske ,  Xeno S. Kovah ,  Nikolaj Schlej ,  Jeffrey R. Wilcox ,  Hardik K. Doshi ,  Kevin H. Alderfer ,  Corey T. Kallenberg

IPC: G06F21/57 ,  G06F9/44 ,  G06F21/79

CPC classification number: G06F21/575 ,  G06F9/4401 ,  G06F21/73 ,  G06F21/79

Abstract: A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor includes a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.

公开(公告)号：US20180088961A1

公开(公告)日：2018-03-29

申请号：US15285202

申请日：2016-10-04

Applicant: Apple Inc.

Inventor： Hardik K. Doshi

IPC: G06F9/44 ,  G06F1/32

CPC classification number: G06F9/4405 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/4418 ,  G06F9/442 ,  Y02D10/122 ,  Y02D10/171

Abstract: A computing device may comprise a first processor and a secondary processor. The first processor may initiate a power management process transitioning the first processor from a first state to a second state and, upon reaching a predetermined step in the power management process, notify the secondary processor of the power management process. The secondary processor may initiate, in response to the notifying, a parallel power management process transitioning the secondary processor from an equivalent first state to an equivalent second state.

公开(公告)号：US11726835B2

公开(公告)日：2023-08-15

申请号：US16872685

申请日：2020-05-12

Applicant: Apple Inc.

Inventor： Michael W. Murphy ,  Gopal Thirumalai Narayanan ,  Deepak K. Mishra ,  Andre M. Glover ,  Sreenivas Tallam ,  Hardik K. Doshi

IPC: G06F9/50 ,  G06F13/42 ,  G06F13/40 ,  H04L47/125

CPC classification number: G06F9/5083 ,  G06F9/505 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4221 ,  G06F13/4282 ,  H04L47/125 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: A method and apparatus of a device that load balances a first plurality of Peripheral Connect Interconnect ports is described. In an exemplary embodiment, the device detects a second plurality of PCI ports in the device. In addition, the device determines a load for each port in the first and second plurality of PCI ports and sorts the second plurality of PCI ports. The device further load balances the first plurality of PCI ports using at least a PCIe switch and the load determination of the second plurality of PCI ports. The device additionally communicates data between the first and second plurality of PCI ports.

公开(公告)号：US10795427B2

公开(公告)日：2020-10-06

申请号：US15720916

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Hardik K. Doshi ,  Gopal Thirumalai Narayanan ,  Siddharth P. Shah ,  Joseph J. Castro ,  Craig S. Forbell ,  Christopher M. Aycock ,  Varaprasad V. Lingutla

IPC: G06F1/3287 ,  G06F1/3206 ,  G06F9/4401

Abstract: A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.

公开(公告)号：US10417429B2

公开(公告)日：2019-09-17

申请号：US15721502

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Joshua P. de Cesare ,  Timothy R. Paaske ,  Xeno S. Kovah ,  Nikolaj Schlej ,  Jeffrey R. Wilcox ,  Hardik K. Doshi ,  Kevin H. Alderfer ,  Corey T. Kallenberg

IPC: G06F21/57 ,  G06F21/79 ,  G06F9/4401

Abstract: A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor includes a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.

公开(公告)号：US20180348850A1

公开(公告)日：2018-12-06

申请号：US15720916

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Hardik K. Doshi ,  Gopal Thirumalai Narayanan ,  Siddharth P. Shah ,  Joseph J. Castro ,  Craig S. Forbell ,  Christopher M. Aycock ,  Varaprasad V. Lingutla

IPC: G06F1/32 ,  G06F9/44 ,  G06F13/42

Abstract: A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.