公开(公告)号：US20210279557A1

公开(公告)日：2021-09-09

申请号：US16810675

申请日：2020-03-05

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Waleed Abdulla ,  Chaminda N. Vidanagamachchi ,  Yohan Rajan

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.