Mappable filter for neural processor circuit

    公开(公告)号:US12141679B2

    公开(公告)日:2024-11-12

    申请号:US17065428

    申请日:2020-10-07

    Applicant: Apple Inc.

    Abstract: Embodiments relate to a neural processor circuit that may include a fetch circuit that fetches coefficient data of a machine learning model from a memory source. The neural processor circuit may also include one or more neural engine circuits that are coupled to the fetch circuit. A neural engine circuit may include a buffer circuit that stores the coefficient data. The neural engine circuit may also include a coefficient organizing circuit that generates at least a first mapping and a second mapping of the stored coefficient data according to one or more control signals. The neural engine may also include a computation circuit that receives and processes at least a portion of input data with the coefficient data as mapped according to the first mapping or process at least the portion of the input data with the coefficient data as mapped according to the second mapping.

    Visual marker
    2.
    发明授权

    公开(公告)号:US11755854B2

    公开(公告)日:2023-09-12

    申请号:US17350515

    申请日:2021-06-17

    Applicant: Apple Inc.

    CPC classification number: G06K7/10722 G06K7/1417 G06K19/0614 G06K19/06037

    Abstract: Various implementations disclosed herein include multi-scale visual markers that convey information in multiple sets of markings using different respective appearance attributes. In some implementations, the appearance attribute of the markings of a first set of markings corresponds to a first encoding parameter and the appearance attribute of markings of a second set of markings corresponds to a second encoding parameter different from the first encoding parameter. In some implementations, the first set of markings encode first data and the second set of markings are different than the first set of markings and encode second data. In some implementations, the different appearance attributes are different scales (e.g., different sizes, different numbers of markings per unit of space, different contrast, different color characteristics, different wavelengths, different image sensor types, etc.).

    System for improving user input recognition on touch surfaces

    公开(公告)号:US12216833B1

    公开(公告)日:2025-02-04

    申请号:US18355006

    申请日:2023-07-19

    Applicant: Apple Inc.

    Abstract: A physical keyboard can be used to collect user input in a typing mode or in a tracking mode. To use a tracking mode, first movement data is detected for a hand of a user in relation to a physical keyboard at a first location. A determination is made that the first movement data is associated with a tracking movement. In response to determining that the movement type is associated with the tracking movement, a tracking mode is initiated. User input is provided based on the movement data and in accordance with the tracking mode. Contact data and non-contact data is used to determine a user intent, and a user instruction is processed based on the user intent.

    MAPPABLE FILTER FOR NEURAL PROCESSOR CIRCUIT

    公开(公告)号:US20220108155A1

    公开(公告)日:2022-04-07

    申请号:US17065428

    申请日:2020-10-07

    Applicant: Apple Inc.

    Abstract: Embodiments relate to a neural processor circuit that may include a fetch circuit that fetches coefficient data of a machine learning model from a memory source. The neural processor circuit may also include one or more neural engine circuits that are coupled to the fetch circuit. A neural engine circuit may include a buffer circuit that stores the coefficient data. The neural engine circuit may also include a coefficient organizing circuit that generates at least a first mapping and a second mapping of the stored coefficient data according to one or more control signals. The neural engine may also include a computation circuit that receives and processes at least a portion of input data with the coefficient data as mapped according to the first mapping or process at least the portion of the input data with the coefficient data as mapped according to the second mapping.

    DYNAMIC VARIABLE BIT WIDTH NEURAL PROCESSOR
    5.
    发明公开

    公开(公告)号:US20230206050A1

    公开(公告)日:2023-06-29

    申请号:US18114169

    申请日:2023-02-24

    Applicant: Apple Inc.

    CPC classification number: G06N3/063 G06N3/08 G06N3/04

    Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.

    System for Improving User Input Recognition on Touch Surfaces

    公开(公告)号:US20250130651A1

    公开(公告)日:2025-04-24

    申请号:US19001155

    申请日:2024-12-24

    Applicant: Apple Inc.

    Abstract: A physical keyboard can be used to collect user input in a typing mode or in a tracking mode. To use a tracking mode, first movement data is detected for a hand of a user in relation to a physical keyboard at a first location. A determination is made that the first movement data is associated with a tracking movement. In response to determining that the movement type is associated with the tracking movement, a tracking mode is initiated. User input is provided based on the movement data and in accordance with the tracking mode. Contact data and non-contact data is used to determine a user intent, and a user instruction is processed based on the user intent.

    Dynamic variable bit width neural processor

    公开(公告)号:US12050987B2

    公开(公告)日:2024-07-30

    申请号:US18114169

    申请日:2023-02-24

    Applicant: Apple Inc.

    CPC classification number: G06N3/063 G06N3/04 G06N3/08

    Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.

    VISUAL MARKER
    8.
    发明申请

    公开(公告)号:US20220019752A1

    公开(公告)日:2022-01-20

    申请号:US17350515

    申请日:2021-06-17

    Applicant: Apple Inc.

    Abstract: Various implementations disclosed herein include multi-scale visual markers that convey information in multiple sets of markings using different respective appearance attributes. In some implementations, the appearance attribute of the markings of a first set of markings corresponds to a first encoding parameter and the appearance attribute of markings of a second set of markings corresponds to a second encoding parameter different from the first encoding parameter. In some implementations, the first set of markings encode first data and the second set of markings are different than the first set of markings and encode second data. In some implementations, the different appearance attributes are different scales (e.g., different sizes, different numbers of markings per unit of space, different contrast, different color characteristics, different wavelengths, different image sensor types, etc.).

    Dynamic variable bit width neural processor

    公开(公告)号:US11593628B2

    公开(公告)日:2023-02-28

    申请号:US16810675

    申请日:2020-03-05

    Applicant: Apple Inc.

    Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.

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