公开(公告)号：US20020117399A1

公开(公告)日：2002-08-29

申请号：US09792737

申请日：2001-02-23

Applicant: Applied Materials, Inc.

Inventor： Fusen Chen ,  Ling Chen

IPC: B32B009/00 ,  H01L021/283 ,  C25D005/02 ,  C23C028/02 ,  C23C028/00 ,  B32B027/14 ,  B32B003/00 ,  B32B007/00

CPC classification number: H01L21/76844 ,  C23C14/165 ,  C23C14/3407 ,  C23C16/45525 ,  C23C28/00 ,  C25D7/123 ,  H01J37/026 ,  H01J2237/0047 ,  H01J2237/3175 ,  H01L21/2855 ,  H01L21/28562 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76865 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/24802 ,  Y10T428/24917 ,  Y10T428/265 ,  H01L2924/00

Abstract: A method of forming a copper via and the resultant structure. A thin layer of an insulating barrier material, such as aluminum oxide or tantalum nitride, is conformally coated onto the sides and bottom of the via hole, for example, by atomic layer deposition (ALD) to a thickness of less than 5 nm, preferably less than 2 nm and having an electrical resistivity of more than 500 microohm-cm. A copper seed layer is then deposited under conditions such that copper is deposited on the via sidewalls but not deposited over most of the bottom of via hole. Instead energetic copper ions sputter the barrier material from the via bottom. Copper is electroplated into the via hole lined only on its sidewalls with the barrier. The invention preferably extends also to dual-damascene structures in which the copper seed sputter process sputters the barrier layer from the via bottom but not the trench floor.

Abstract translation: 形成铜通孔的方法和所得结构。 诸如氧化铝或氮化钽的绝缘阻挡材料的薄层例如通过原子层沉积（ALD）共形地涂覆在通孔的侧面和底部上，厚度小于5nm，优选地 小于2nm并且具有大于500微欧姆·厘米的电阻率。 然后在使得铜沉积在通孔侧壁上但不沉积在通孔的大部分底部的条件下沉积铜籽晶层。 相反，高能铜离子从通孔底部溅射阻挡材料。 将铜电镀到仅在其侧壁上排列的通孔中。 本发明还优选地延伸到双镶嵌结构，其中铜种子溅射处理从通孔底部而不是沟槽底部喷射阻挡层。

公开(公告)号：US20040222082A1

公开(公告)日：2004-11-11

申请号：US10429941

申请日：2003-05-05

Applicant: APPLIED MATERIALS, INC.

Inventor： Praburam Gopalraja ,  Xianmin Tang ,  Jianming Fu ,  Mark A. Perrin ,  Jean Yue (Phillip) Wang ,  Arvind Sundarrajan ,  Hong Zhang ,  Jick Yu ,  Umesh Kelkar ,  Zheng Xu ,  Fusen Chen

IPC: C23C014/32 ,  G21G005/00

CPC classification number: H01J37/34 ,  C23C14/046 ,  C23C14/3442 ,  C23C14/5833 ,  H01J37/3053 ,  H01L21/2855 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865

Abstract: In conjunction with sputtering a metal, especially copper, into high aspect-ratio holes in a wafer, an oblique ion milling method in which argon ions or other particles having energies in the range of 200 to 1500 eV are directed to the wafer at between 10 and 35null to the wafer surface to sputter etch material sputter deposited preferentially on the upper corners of the holes. The milling may be performed in the sputter deposition chamber either simultaneously with the deposition or after it or performed afterwards in a separate milling reactor. A plurality of ion sources arranged around the chamber improve angular uniformity or arranged axially improve radial uniformity or vary the angle of incidence. An annular ion source about the chamber axis allows a plasma current loop. Anode layer ion sources and sources composed of copper are advantageous.

Abstract translation: 结合将金属，特别是铜溅射到晶片中的高纵横比孔中，其中具有在200至1500eV范围内的能量的氩离子或其它颗粒的倾斜离子研磨方法在10 并且与晶片表面成35°的溅射蚀刻材料溅射沉积优先在孔的上角上。 铣削可以在溅射沉积室中同时进行沉积，或在其之后或之后在单独的研磨反应器中进行。 围绕腔室布置的多个离子源提高了角度均匀性或者轴向地改变径向均匀性或改变入射角。 围绕腔室轴线的环形离子源允许等离子体电流回路。 阳极层离子源和由铜组成的源是有利的。

公开(公告)号：US20040140196A1

公开(公告)日：2004-07-22

申请号：US10346974

申请日：2003-01-17

Applicant: Applied Materials, Inc.

Inventor： Praburam Gopalraja ,  Jianming Fu ,  Xianmin Tang ,  Fusen Chen

IPC: C23C014/00 ,  C23C014/32

CPC classification number: H01L21/76844 ,  C23C14/046 ,  C23C14/3492 ,  C23C14/35 ,  C23C14/54 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sputter deposition method is performed in a sputtering chamber having a sputtering target facing a substrate support. A substrate is placed on the support in the chamber and, in a first sputtering stage, a first layer of sputtered material is deposited on the substrate by maintaining a first pressure of a sputtering gas in the chamber, and maintaining the substrate support at a first bias power level. In a second sputtering stage, a second layer of sputtered material is deposited on the substrate by maintaining a second pressure of the sputtering gas that is lower than the first pressure, and maintaining the substrate support at a second bias power level that is higher than the first bias power level.

Abstract translation: 在具有面向衬底支撑体的溅射靶的溅射室中进行溅射沉积方法。 将衬底放置在腔室中的支撑体上，并且在第一溅射阶段中，通过在腔室中保持溅射气体的第一压力将第一层溅射材料沉积在衬底上，并将衬底支撑件保持在第一 偏置功率电平。 在第二溅射阶段，通过保持低于第一压力的溅射气体的第二压力将第二溅射材料层沉积在衬底上，并且将衬底支撑件保持在高于第一压力的第二偏压功率水平 第一偏置功率电平。

公开(公告)号：US20030013297A1

公开(公告)日：2003-01-16

申请号：US10245104

申请日：2002-09-16

Applicant: APPLIED MATERIALS, INC.

Inventor： Fusen Chen ,  Liang-Yuh Chen ,  Roderick Craig Mosely ,  Moshe Eizenberg

IPC: H01L021/4763

CPC classification number: H01L21/76804 ,  C25D5/02 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a process sequence and related hardware for filling a hole with copper. The sequence comprises first forming a reliable barrier layer in the hole to prevent diffusion of the copper into the dielectric layer through which the hole is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the bottom of the hole, depositing a second barrier, and then filling the hole with copper. An alternative sequence comprises depositing a first barrier layer over a blanket dielectric layer, forming a hole through both the barrier layer and the dielectric layer, depositing a generally conformal second barrier layer in the hole, removing the barrier layer from the bottom of the hole, and selectively filling the hole with copper.

Abstract translation: 本发明提供了用铜填充孔的工艺顺序和相关硬件。 该顺序包括首先在孔中形成可靠的阻挡层，以防止铜扩散到形成孔的电介质层中。 一个序列包括在图案化电介质上形成大致保形的阻挡层，蚀刻孔的底部，沉积第二屏障，然后用铜填充孔。 替代的顺序包括在覆盖的介电层上沉积第一阻挡层，通过阻挡层和电介质层两者形成孔，在孔中沉积大致保形的第二阻挡层，从孔的底部去除阻挡层， 并用铜选择性地填充孔。

公开(公告)号：US20020192948A1

公开(公告)日：2002-12-19

申请号：US09882696

申请日：2001-06-15

Applicant: Applied Materials, Inc.

Inventor： Fusen Chen ,  Ling Chen ,  Gongda Yao ,  Ming Xi ,  Barry Chin ,  Mei Chang ,  Seshadri Ganguli ,  Michael X. Yang ,  Hyungsuk Alexander Yoon

IPC: H01L021/4763 ,  H01L021/44

CPC classification number: H01L21/76846 ,  H01L21/2855 ,  H01L21/28556

Abstract: A method of forming a composite barrier layer structure for use in integrated circuits is disclosed. The composite barrier layer structure formed using both physical vapor deposition (PVD) and chemical vapor deposition (CVD) techniques. The composite barrier layer structure comprises a CVD deposited layer formed on a PVD deposited layer. During the PVD process, the underlying surface of the substrate is treated, reducing the resistivity of the barrier layer structure formed thereon.

Abstract translation: 公开了一种形成用于集成电路的复合势垒层结构的方法。 使用物理气相沉积（PVD）和化学气相沉积（CVD）技术形成的复合阻挡层结构。 复合势垒层结构包括形成在PVD沉积层上的CVD沉积层。 在PVD工艺期间，处理衬底的下表面，降低其上形成的阻挡层结构的电阻率。